PM3350 ELAN 8 X10
ELAN 8X10
DATA SHEET
PMC-970109
ISSUE 3
8 PORT ETHERNET SWITCH
Receive collision detect signals. These inputs pass the collision detect and SQE
test signals generated by the external MAU devices to the ELAN 8x10. They are
sampled synchronously to the TCLK[7:0] clock references (COL[0] corresponds
to TCLK[0], and so on), and should be asserted by the MAU devices to indicate
collisions on the medium as well as to signal a successful SQE test after
transmit. If not all of the 8 collision signal inputs are connected to external MAU
devices, the unused inputs should be tied LOW.
COL[7:0]
8
1
I
MAU loopback mode select (all 8 ports). This pin can be left as a no-connect
or wired to the loopback mode input of an attached PHY device. The loopback
mode feature on the PM3350 is not operational. Hence, this pin has no implied
functionality.
LBK
O
Local Memory Interface
Signal Name
Size
Type Description
Memory data bus. MDATA[31:0] carries the data driven to the external local
memory by the ELAN 8x10 during local memory writes, and the data sent back
to the ELAN 8x10 by the memory devices during local memory reads. In
addition, configuration information is latched from the MDATA[31:0] lines
during ELAN 8x10 reset and loaded into an internal configuration register;
either pullup-pulldown resistors or tri-state buffers (enabled by the RST* input)
drive configuration data on to the MDATA[31:0] lines during reset.
MDATA[31:0]
32
I/O
All MDATA[31:0] pins have internal pullups.
Memory address bus; supplies a word-aligned address to the external memory
devices (i.e., address bits 22 through 2 of the 24-bit byte address generated by
the internal ELAN 8x10 logic), and thus selects a single 32-bit word to be read
or written. Up to 4 MB of memory may be directly addressed in each bank
using these address lines. In addition, the lower 11 bits of MADDR[19:0] (i.e.,
MADDR[10:0]) carry a multiplexed row/column address when DRAM accesses
are being made, with the row address being presented when MRAS_ is high
and the column address being presented when it is low. Multiplexing for 8-, 9-,
10- and 11-bit column addresses is supported. Up to 4 MB of memory may be
addressed in each bank when multiplexing is enabled for that bank (i.e., by
configuring the bank for DRAM accesses).
MADDR[19:0]
20
O
Memory bank chip selects. The MCS_[3:0] outputs select one of four memory
banks; each bank is 4 megabytes in size. They are decoded directly from the
most significant 2 bits (bits 23 and 22) of the 24-bit physical byte address
generated by the internal ELAN 8x10 logic, and are synchronous to MEMCLK.
When driving DRAM memory devices other than 2-CAS DRAMs, the
MCS_[3:0] signals function as the Column Address Strobe (CAS) signals to the
memories.
MCS_[3:0]
4
1
O
O
DRAM Row Address Strobe output; supplies the Row Address Strobe (RAS)
signal to one or more external DRAM banks. It is asserted to latch the row
address supplied on the MADDR lines into the DRAM array, and allow the
column address to be output one cycle later. It may be tied directly to the RAS*
inputs of standard asynchronous DRAM devices.
MRAS_
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND PMC-SIERRA, INC. CUSTOMERS ONLY
24
PMC [ PMC-SIERRA, INC ]
