Data Book
PLX Technology, Inc.
Terms and
Abbreviations
Definitions
A functional unit that provides the PCI Express conforming system interface. Includes the
Serializer and De-serializer (SerDes) hardware interface modules and PCI Express Interface,
which provides the Physical Layer, Data Link Layer, and Transaction Layer logic.
PCI Express
Station
PHY
Port
Physical Layer.
Ports are a collection of lanes configured at startup which contain the functional logic
and memory resources to communicate with like resources in other PCI Express devices.
PRBS
QoS
Pseudo-Random Bit Sequence.
Quality of Service.
RAS
RoHS
RR
Reliability, Availability, and Serviceability.
Restrictions on the use of certain Hazardous Substances (RoHS) Directive.
Round-Robin scheduling.
Serializer/De-serializer. A high-speed differential-signaling parallel-to-serial and
serial-to-parallel conversion logic attached to lane pads.
SerDes
TC
Traffic Class.
TDM
Time Division Multiplexing.
Transaction Layer Control. The module performing PCI Express Transaction Layer
functions.
TLC
TLP
Transaction Layer Packet. PCI-Express packet formation and organization.
Refers to standard PCI Express upstream-to-downstream routing protocol.
Transparent
Upstream station. Contains the component’s upstream port. An upstream station can contain
downstream ports.
Upstream station
VC
Virtual Channel.
Virtual Interface
WRR
Secondary side of the NT port, connects to the internal virtual PCI Express interface.
Weighted Round-Robin scheduling.
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ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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