February, 2007
Revision History
Revision History
Version
Date
Description of Changes
Production Release, Silicon Revisions AA and BA.
Includes JTAG, power, and ordering information for Silicon Revision AA.
All information pertains to AA and BA devices, unless indicated otherwise
as PEX 8532AA or PEX 8532BA.
1.0
1.1
October, 2005
October, 2005
Chapter 9, “Hot Plug”: Removed watermark, and changed “8516” to “8532” in text.
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Production Release, Silicon Revision BB, and updates to AA and BA
Changed EHBGA to Plastic BGA / PBGA
Corrected signal type listed for PEX_REFCLKn/p
Revised SerDes-related content to more specifically reference related lanes,
ports, and stations
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Removed plural references to upstream ports
Removed references to Promiscuous mode.
Section 8.2.2, “Port-to-Station Aggregation” – Corrected to indicate correct
combined port width for a single station
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Section 12.1.2.2, “Intelligent Adapter Mode NT Port Reset” – Changed “1 ms”
to “1 µs” in second paragraph
Register 11-8, offset 1Ch[31] – Corrected cross-reference to indicate the Parity
Error Response Enable bit
1.2
February, 2006
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Register 11-49, offset 1CCh[13] – Corrected value of 1 to indicate > 8
Corrected Table 17-1 title to indicate field value of 10b
Table A-1, “Serial EEPROM Memory Map”– Corrected addresses for Link Port
offsets DF4h and DF8h, and Virtual Port offsets DE0h through FDCh
Table A-1, “Serial EEPROM Memory Map”– Marked B80h - B88h, B98h, and
B9Ch as Reserved, and hyperlinked all register names in the “Register Name”
column to the register names in their respective chapters
Miscellaneous changes for readability
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Figure 3-1 – Clarified view as “See-Through Top View”
Table 3-8 – Removed Hot Plug balls from N/C listing (J34, K34, L34, M34, N34,
P34, R34, T34, U34, V34, W34, Y34, AA34, AB34, AC34, AD34, AE34, AF34)
Section 5.1.3.1 – Changed “upstream and downstream stations” to “upstream and
downstream ports”
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Section 5.2.5, “Reset and Clock Initialization Timing” – Created new heading,
to include table and figure
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Table 8-1 – Moved to “RAM and Queue Size” section
Figure 9-3 – Corrected HP_PERST# signal to be high
Chapter 11, register offset 1D0h – Changed “Reserved” reference
to “Factory Test Only”
1.3
June, 2006
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Section 12.4 – Changed “upstream port” reference to “downstream ports”
Chapters 15 and 16 – Changed “corresponding port” references to appropriate
NT Port interface
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Section 17.1.7 – Removed reference to reserved registers for Station 1
Tables 17-3, 17-4, and 17-5 – Merged JTAG IDCODE content into a single table,
Table 17-3
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Appendix B – Updated Product Ordering table
Miscellaneous changes for readability
1.4
1.5
August, 2006
January, 2007
Miscellaneous changes, corrections, and enhancements throughout the data book.
Rewrote Chapter 18, “Electrical Specifications.”
Updated RDK ordering information in Appendix B, “General Information.”
Production Release, Silicon Revision BC.
1.6
February, 2007
Miscellaneous changes, corrections, and enhancements throughout the data book.
Moved Table A-2 content into Table A-1.
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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PLX [ PLX TECHNOLOGY ]
