February, 2007
Terms and Abbreviations
Note: In this data book, shortened titles are associated with the previously listed documents.
The following table lists these abbreviations.
Abbreviation
Document
PCI r2.3
PCI Local Bus Specification, Revision 2.3
PCI Power Mgmt. r1.1
PCI-to-PCI Bridge r1.1
Hot Plug r1.1
PCI Bus Power Management Interface Specification, Revision 1.1
PCI to PCI Bridge Architecture Specification, Revision 1.1
PCI Hot Plug Specification, Revision 1.1
PCI Standard Hot Plug Controller and Subsystem Specification,
Revision 1.0
PCI Standard Hot Plug Controller
and Subsystem r1.0
PCI Express Base r1.0a
PCI Express CEM r1.0a
IEEE Standard 1149.1-1990
PCI Express Base Specification, Revision 1.0a
PCI Express Card Electromechanical (CEM) Specification, Revision 1.0a
IEEE Standard Test Access Port and Boundary-Scan Architecture
IEEE Standard 1149.6-2003, IEEE Standard Test Access Port and
Boundary-Scan Architecture Extensions
IEEE Standard 1149.6-2003
Terms and Abbreviations
The following table lists common terms and abbreviations used in this data book. Terms and
abbreviations defined in the PCI Express Base r1.0a are not included in this table.
Terms and
Definitions
Abbreviations
Address mapping CAM that determines a memory request route. Contains mirror copies of
the PCI-to-PCI Bridges Memory Base and Limit registers in the switch.
AMCAM
Bus Number mapping CAM that determines the completion route. Contains mirror copies of
the PCI-to-PCI Bridges Secondary Bus-Number and Subordinate Bus-Number registers in
the switch.
BusNoCAM
CAM
CSRs
Content Addressable Memory.
Configuration Space registers.
Downstream
Station
A station that contains only downstream ports.
•
•
Egress – Outgoing traffic from chip
Egress queue – Egress queuing/scheduling mechanism
Egress queue
GPIO
General-Purpose Input/Output.
•
•
Ingress – Incoming traffic to chip
Ingress queue – Ingress queuing/scheduling mechanism
Ingress queue
I/O Address mapping CAM that determines an I/O request route. Contains mirror copies
of the PCI-to-PCI Bridges I/O Base and Limit registers in the switch.
IOAMCAM
Lane
Lanes are comprised of a bi-directional pair of differential PCI Express I/O signals.
Primary side of the NT port, connects to external device pins. The secondary side of the NT
port is referred to as the NT Port Virtual Interface, and connects to the internal virtual PCI
Express interface.
Link Interface
Local
Reference to PCI Express attributes (such as, credits) that belong to the PCI Express station.
A bridging technique used in the PCI Express Switch to isolate memory spaces by presenting
the processor as an endpoint rather than another memory system.
Non-Transparent
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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