PEX 8532 Transparent Mode Port Registers
PLX Technology, Inc.
Register 11-23. 68h PCI Express Capability List and Capabilities (All Ports)
Serial
Default
Bit(s)
Description
Ports
PCI Express Capability List
Type
EEPROM
Capability ID
7:0
RO
RO
Yes
Yes
10h
00h
Set to 10h, as required by the PCI Express Base r1.0a.
Next Capability Pointer
00h = PCI Express Capability is the last capability in the PEX 8532 port
Capabilities list
15:8
The PEX 8532 port Extended Capabilities list starts at 100h.
PCI Express Capabilities
Capability Version
19:16
23:20
RO
Yes
1h
The PEX 8532 ports sets this field to 1h, as required by the
PCI Express Base r1.0a.
Upstream
RO
RO
Yes
Yes
5h
6h
Device/Port Type
Set at reset, as required by the PCI Express Base r1.0a.
Downstream
Slot Implemented
Upstream
RO
No
0
0 = Disables or connects to an upstream port
0 = Disables or connects to an integrated componenta
24
1 = Indicates that the downstream port connects to a slot, as
opposed to being connected to an integrated component or
being disabled
Downstream
RO
Yes
1
Interrupt Message Number
29:25
RO
Yes
0000_0b
00b
The serial EEPROM writes 0000_0b, because the Base message
and MSI messages are the same.
31:30 Reserved
a. The PEX 8532 Serial EEPROM register initialization capability is used to change this value to 0h, indicating that
the corresponding PEX 8532 downstream port connects to an integrated component or is disabled.
174
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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