9.2.2
ISA Mode...................................................................................................................................
60
9.3
M
EMORY
A
DDRESS
D
ECODING
............................................................................................................ 60
9.3.1
Memory-Mapped I/O Base and Limit Address Registers
.......................................................... 61
10
10.1
10.2
11
12
PCI BUS ARBITRATION
................................................................................................................. 62
P
RIMARY
PCI B
US
A
RBITRATION
......................................................................................................... 62
S
ECONDARY
PCI B
US
A
RBITRATION
.................................................................................................... 62
TRANSACTION DELAY
.................................................................................................................. 63
ERROR HANDLING
........................................................................................................................ 64
12.1 A
DDRESS
P
ARITY
E
RRORS
.................................................................................................................. 64
12.2 D
ATA
P
ARITY
E
RRORS
........................................................................................................................ 65
12.2.1 Configuration Write Transactions to Configuration Space
........................................................ 65
12.2.2 Read Transactions
.................................................................................................................... 65
12.3 D
ATA
P
ARITY
E
RROR
R
EPORTING
S
UMMARY
....................................................................................... 66
12.4 S
YSTEM
E
RROR
(SERR#) R
EPORTING
............................................................................................... 69
13
13.1
13.2
14
RESET..............................................................................................................................................
70
P
RIMARY
I
NTERFACE
R
ESET
............................................................................................................... 70
S
ECONDARY
I
NTERFACE
R
ESET
.......................................................................................................... 70
BRIDGE BEHAVIOR
....................................................................................................................... 71
14.1 A
BNORMAL
T
ERMINATION
(I
NITIATED BY
B
RIDGE
M
ASTER
)
................................................................... 72
14.1.1 Master Abort..............................................................................................................................
72
14.1.2 PCI Master on Primary Bus.......................................................................................................
72
14.2 C
ONFIGURATION
T
YPE
#1
TO TYPE
#0 C
ONVERSION
........................................................................... 72
14.3 C
ONFIGURATION
T
YPE
#1
TO
T
YPE
#1 B
Y
-P
ASSING
............................................................................ 73
14.4 T
YPE
-0 C
ONFIGURATION
C
YCLE
F
ILTER
M
ODE
.................................................................................... 73
14.5 D
ECODING
......................................................................................................................................... 73
14.6 S
ECONDARY
M
ASTER
......................................................................................................................... 74
14.7 PCI C
LOCK
R
UN
F
EATURE
.................................................................................................................. 74
15
15.1
15.2
16
17
CLOCKS
.......................................................................................................................................... 75
P
RIMARY AND
S
ECONDARY
C
LOCK
I
NPUTS
.......................................................................................... 75
S
ECONDARY
C
LOCK
O
UTPUTS
............................................................................................................ 75
66-MHZ OPERATION
...................................................................................................................... 76
MISCELLANEOUS OPTIONS
......................................................................................................... 77
17.1 EEPROM I
NTERFACE
........................................................................................................................ 77
17.1.1 Auto Mode EEPROM Access....................................................................................................
77
17.1.2 EEPROM Mode at Reset
.......................................................................................................... 77
17.1.3 EEPROM Data Structure
.......................................................................................................... 78
17.1.4 EEPROM Address and Corresponding PCI 6152 Register
...................................................... 79
17.2 G
ENERAL
P
URPOSE
I/O I
NTERFACE
.................................................................................................... 80
17.3 V
ITAL
P
RODUCT
D
ATA
........................................................................................................................ 80
18
19
19.1
19.2
PCI POWER MANAGEMENT..........................................................................................................
81
HOT SWAP
...................................................................................................................................... 82
H
OT
S
WAP
I
NSERTION
........................................................................................................................ 82
H
OT
S
WAP
E
XTRACTION
..................................................................................................................... 82
PCI 6152 Data Book v2.0
2003 PLX Technology, Inc. All rights reserved.
8
PLX [ PLX TECHNOLOGY ]
