Contents
HISTORY ...................................................................................................................................................... 6
1
2
3
4
5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
6
REGISTER INDEX...............................................................................................................................
11
INTRODUCTION
................................................................................................................................. 12
ORDERING INFORMATION
............................................................................................................... 12
PIN DIAGRAM
..................................................................................................................................... 13
SIGNAL DEFINITION
.......................................................................................................................... 14
P
RIMARY
B
US
I
NTERFACE
S
IGNALS
..................................................................................................... 14
S
ECONDARY
B
US
I
NTERFACE
S
IGNALS
................................................................................................ 16
C
LOCK
S
IGNALS
................................................................................................................................. 17
R
ESET
S
IGNALS
................................................................................................................................. 17
H
OT
S
WAP
S
IGNALS
........................................................................................................................... 17
M
ISCELLANEOUS
S
IGNALS
.................................................................................................................. 18
P
OWER
S
IGNALS
................................................................................................................................ 18
PIN ASSIGNMENT
.............................................................................................................................. 19
6.1
PCI 6152 P
INOUT
T
ABLES
.................................................................................................................. 20
6.1.1
Pin Assignment Sorted by Location
.......................................................................................... 20
6.1.2
Pin Assignment Sorted by Signal Name
................................................................................... 22
7
7.1
7.2
8
CONFIGURATION REGISTERS.........................................................................................................
24
C
ONFIGURATION
S
PACE
M
AP
– T
RANSPARENT
M
ODE
.......................................................................... 24
C
ONFIGURATION
R
EGISTER
D
ESCRIPTION
........................................................................................... 26
PCI BUS OPERATION
........................................................................................................................ 45
8.1
T
YPES OF
T
RANSACTIONS
................................................................................................................... 45
8.2
A
DDRESS
P
HASE
................................................................................................................................ 46
8.3
D
EVICE
S
ELECT
(DEVSEL_L) G
ENERATION
....................................................................................... 46
8.4
D
ATA
P
HASE
...................................................................................................................................... 46
8.5
W
RITE
T
RANSACTIONS
....................................................................................................................... 47
8.6
R
EAD
T
RANSACTIONS
......................................................................................................................... 47
8.7
C
ONFIGURATION
T
RANSACTIONS
......................................................................................................... 48
8.7.1
Type 0 Access to PCI 6152.......................................................................................................
48
8.7.2
Type 1 to Type 0 Translation
.................................................................................................... 49
8.7.3
Type 1 to Type 1 Forwarding
.................................................................................................... 51
8.7.4
Special Cycles...........................................................................................................................
52
8.8
T
RANSACTION
T
ERMINATION
............................................................................................................... 53
8.8.1
Master Termination Initiated by PCI 6152.................................................................................
53
8.8.2
Master Abort Received by PCI 6152.........................................................................................
54
8.8.3
Target Termination Received by PCI 6152
............................................................................... 54
8.8.4
Target Termination Initiated by PCI 6152
................................................................................. 57
9
ADDRESS DECODING
....................................................................................................................... 58
9.1
A
DDRESS
R
ANGES
............................................................................................................................. 58
9.2
I/O A
DDRESS
D
ECODING
.................................................................................................................... 58
9.2.1
I/O Base and Limit Address Registers
...................................................................................... 59
PCI 6152 Data Book v2.0
2003 PLX Technology, Inc. All rights reserved.
7
PLX [ PLX TECHNOLOGY ]
