History
Revision
1.1
1.2
1.3
1.4
1.5
Date
3/27/01
4/9/01
4/24/01
4/30/01
7/12/01
Description
Corrected register C4h, bit 4,5 description. Default should be 2 clocks delay.
Updated Company Address
Corrected description of register 28h and 2Ch register.
Updated Revision ID description at register 8h.
Enhanced EEPROM Section description.
This release reflects PLX part numbering.
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2.0
05/28/03
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Changed “SRST_L to “S_RST_L”, 3 places, in Register 3Eh
Changed Register 82h, bits 11-15 description
Changed Dual Address Cycle (1101) values from “N” to “Y” in Table 8-1
Globally changed LDEV, LDEV#, and DEVSEL to DEVSEL_L
Changed Case 1 and 3 descriptions in Section 8.6
Removed secondary clock information from bullet 2 and S_RST# bullets (4 and 6 )
from Section 13.2
Updated Master on primary and secondary response in Section 14
Removed synchronous design information from Section 16
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PCI 6152 Data Book v2.0
2003 PLX Technology, Inc. All rights reserved.
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PLX [ PLX TECHNOLOGY ]
