(Preliminary)PL610-01
1.8V to 3.3V, 1MHz to 130MHz XO IC
FUNCTIONAL DESCRIPTION
PL610-01 is a highly featured, very flexible, advanced XO design for high performance, low-power, small form-
factor applications. The PL610-01 accepts a fundamental input crystal of 5MHz to 130MHz or a reference clock
input of 1MHz to 130MHz and is capable of producing two outputs up to 130MHz. This flexible design allows the
PL610-01 to deliver any frequency, FREF (Crystal or Ref Clk) frequency, FREF / 2 or FREF / P to CLK0 and/or
CLK1. Some of the design features of the PL610-01 are mentioned below:
Clock Output (CLK0)
Power-Down Control (PDB)
CLK0 is the main clock output. The output from CLK0
can be FREF (Crystal or Ref Clk), FREF/2 or FREF/P
output. The output drive level can be programmed to
Low Drive (4mA), Standard Drive (8mA) or High Drive
(16mA).
The Power Down (PDB) feature allows the user to
put the PL610-01 into “Sleep Mode”. When
activated (logic ‘0’), PDB ‘Disables the PLL, the
oscillator circuitry, counters, and all other active
circuitry. In Power Down mode the IC consumes
<10µA of power. The PDB pin incorporates a 10MΩ
pull up resistor giving a default condition of logic “1”.
Programmable I/O (OE/PDB/CLK1)
The PL610-01provides one programmable I/O pin
which can be configured as one of the following
functions:
Clock Output (CLK1)
The CLK1 feature allows the PL610-01 to have an
additional clock output programmed to one of the
following:
Output Enable (OE)
FREF - Reference (Crystal or Ref Clk)
Frequency
FREF / 2
The Output Enable feature allows the user to enable
and disable the clock output(s) by toggling the OE
pin. The OE pin incorporates a 60kΩ pull up
resistor giving a default condition of logic “1”.
CLK0
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 4/2/07 Page 3
PLL [ PHASELINK CORPORATION ]
