(Preliminary)PL610-01
1.8V to 3.3V, 1MHz to 130MHz XO IC
KEY PROGRAMMING PARAMETERS (Optional)
CLK[0:1]
Output Frequency
Programmable
Input/Output
Output Drive Strength
FOUT = FREF / P*
Three optional drive strengths One output pin can be configured
(*: P is an Odd/Even Divider)
Where P = 6 bit
to choose from:
as:
OE - input
PDB - input
CLK1 – output
Low: 4mA
Std: 8mA (default)
High: 16mA
CLK0 = FREF, FREF/2 or FREF / P
CLK1 = FREF, FREF/2 or CLK0
PACKAGE PIN AND DIE PAD ASSIGNMENT
Pin Assignment
Name
Type
Description
DFN-6L
SOT23-6L
XIN, FIN
1
3
I
Crystal or Reference Clock input pin
This programmable I/O pin can be configured as an Output
Enable (OE) input, Power Down input (PDB) input or CLK1
clock output. This pin has an internal 60KΩ pull up resistor
for OE and 10MΩ pull up resistor for PDB.
OE, PDB,
CLK1
2
1
I/O
State
OE
PDB
0
Tri-state CLK
Normal mode
Power Down Mode
Normal mode
1 (default)
GND
CLK0
VDD
3
4
5
2
6
5
P
O
P
GND connection
Programmable Clock Output
VDD connection
Crystal Output pin
XOUT
6
4
O
Do Not Connect (DNC ) when FIN is present
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 4/2/07 Page 2
PLL [ PHASELINK CORPORATION ]
