PixArt Imaging Inc.
PAS202BCA/PAS202BBA
CMOS Image Sensor IC
SDA
DATA
CHANGE
ALLOWED
DATA
STABLE
SCL
Fig 4.2 Valid Data
4.2 Data Transfer Format
4.2.1 Master transmits data to slave (write cycle)
§
§
§
§
S : Start
A : Acknowledge by slave
P : Stop
RW : The LSB of 1ST byte to decide whether current cycle is read or write cycle.
RW=1 read cycle, RW=0 write cycle.
§
SUBADDRESS : The address values of PAS202BCA/PAS202BBA internal control registers
(Please refer to PAS202BCA/PAS202BBA register description)
1ST BYTE
2ND BYTE
n BYTEs + A
S
SLAVE ID (7 BIT)
RW
A
SUBADDRESS (8 BIT)
A
DATA
A
DATA
A
P
MSB
LSB=0
st
During write cycle, the master generates start condition and then places the 1 byte data that are combined
slave address (7 bits) with a read/write control bit to SDA line. After slave(PAS202BCA/PAS202BBA) issues
acknowledgment, the master places 2nd byte (sub-address) data on SDA line. Again follow the
PAS202BCA/PAS202BBA acknowledgment, the master places the 8 bits data on SDA line and transmit to
PAS202BCA/PAS202BBA control register (address was assigned by 2nd byte). After
PAS202BCA/PAS202BBA issue acknowledgment, the master can generate a stop condition to end of this
write cycle. In the condition of multi-byte write, the PAS202BCA/PAS202BBA sub-address is automatically
increment after each DATA byte transferred. The data and A cycles is repeat until last byte write. Every control
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PixArt Imaging Inc.
E-mail: fae_service@pixart.com.tw
V1.2, May. 2002
PIXART [ PIXART IMAGING INC. ]
