PixArt Imaging Inc.
PAS005B
CMOS Image Sensor IC
in redundancy rows
Reg_48[5]
Reg_48[4]
CDS_pd
ASP_pd
R/W
R/W
0
0
Analog CDS disable in redundancy rows
Analog signal path disable in redundancy rows
Combination of (single_path, path_chg):
00: even pixels processed by even signal path, odd
pixels processed by odd signal path
01: even pixels processed by odd signal path, odd
pixels processed by even signal path
10: all pixels are processed by the even signal path
11: all pixels are processed by the odd signal path
Useful only when mono mode and double path
readout, even pixels and odd pixels are all processed,
but just only either even or odd pixels are readout
0: for readout even path
Reg_48[3]
path_chg
R/W
0
Reg_48[2]
even_path
R/W
0
1: for readout odd path
Reg_48[1]
Reg_48[0]
Reg_49[5]
Reg_49[4]
Reg_49[3]
Reg_49[2]
Reg_49[1]
Reg_49[0]
Reg_50[5]
Reg_50[4]
Reg_50[3]
Reg_50[2]
Reg_50[1]
Reg_50[0]
Reg_51[7]
Reg_51[6]
Reg_51[5]
Reg_51[4]
Reg_51[3]
Reg_51[2]
Reg_51[1]
Reg_51[0]
Reg_52[5:4]
Reg_52[3:2]
Reg_52[1:0]
Reg_53[6]
Reg_53[5:4]
Reg_53[3:2]
csbE
csbO
Test_EnH
dqio_EnL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1 for closing the even analog signal path
1 for closing the odd analog signal path
Test enable high
dqio enable low
scan_Dac
scan DAC(useful only when Test_EnH=1)
scan Color Gain(useful only when Test_EnH=1)
scan Global Gain(useful only when Test_EnH=1)
pga test enable high
Source follower dynamic switch enable high
Analog signal path offset enable low
Zeroing switch delay plus enable high
Zeroing switch in CDS enable high
VGA resolution averaged out enable high
CIF resolution averaged out enable high
CDS block fast enable high
DAC block fast enable high
PGA block fast enable high
ADC block fast enable high
CDS block enable low
DAC block enable low
PGA block enable low
ADC block enable low
CDS bias current option
VLRST voltage level option
VDDAY voltage level option
Regulator block enable low
Regulator current level option
Reference voltage (VRT-VRB) range option
Internal regulated digital power X_VDDD voltage
level option
0: CDS clock = even path clock
1: CDS clock = odd path clock
scan_Color
scan_Global
pga_test_EnH
sfswt_EnH
offset_EnL
zdly_plus
cds_zero_EnH
vga_ave_EnH
cif_ave_EnH
cds_fast_EnH
dac_fast_EnH
pga_fast_EnH
adc_fast_EnH
cds_EnL
dac_EnL
pga_EnL
adc_EnL
cdsbias[1:0]
vlrst[1:0]
vdday[1:0]
reg_EnL
regfast[1:0]
vrefLG[1:0]
Reg_53[1:0]
Reg_54[7]
Reg_54[6]
vddd[1:0]
T_gp1
R/W
R/W
R/W
0
0
0
0: X_VDDD switch ON diode connect from VDDD
1: X_VDDD switch OFF diode connect from VDDD
External VDDAY enable high
T_gp2
Reg_54[5]
Reg_54[4]
extvdy_EnH
vayNdrv_EnH
R/W
R/W
0
0
VDDAY with NMOS drive enable high
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PixArt Imaging Inc.
E-mail: fae_service@pixart.com.tw
PIXART [ PIXART IMAGING INC. ]
