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PAS005B 参数 Datasheet PDF下载

PAS005B图片预览
型号: PAS005B
PDF下载: 下载PDF文件 查看货源
内容描述: SXGA彩色/黑白数码CMOS图像传感器 [SXGA Color/Mono Digital CMOS Image Sensor]
分类和应用: 传感器图像传感器
文件页数/大小: 41 页 / 1907 K
品牌: PIXART [ PIXART IMAGING INC. ]
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PixArt Imaging Inc.
PAS005B
Reg_30[3:0]
Reg_31[3:0]
Reg_32[3:0]
Reg_33[2:0]
Reg_34[7:0]
Reg_35[2:0]
Reg_36[7:0]
Reg_37[2:0]
Reg_38[7:0]
Reg_39[2:0]
Reg_40[7:0]
Cg_G1[3:0]
Cg_G0[3:0]
Cg_R[3:0]
acc1_B[10:8]
acc1_B[7:0]
acc1_G1[10:8]
acc1_G1[7:0]
acc1_G0[10:8]
acc1_G0[7:0]
acc1_R[10:8]
acc1_R[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CMOS Image Sensor IC
0
0
0
0
0
0
0
0
0
0
0
Color gain of color G1
Color gain of color G0
Color gain of color R
2’s complement value for digital calibration of color
B
2’s complement value for digital calibration of color
G1
2’s complement value for digital calibration of color
G1
2’s complement value for digital calibration of color
G1
2’s complement value for digital calibration of color
G0
2’s complement value for digital calibration of color
G0
2’s complement value for digital calibration of color
R
2’s complement value for digital calibration of color
R
used to synchronize register update by frame when
fast_i2c is set 0
It will be reset to 0 till the first new frame is readout
after it is set to 1
when it is set to 1, the mode related registers will be
updated only after mode_chg is set to 1
DAC & PGA update delay 1 frame automatically
fast update of synchronized i2c registers
source follower reset enable
SHR extension CDS_rst1:
00:
9 ck12
01:
14 ck12
10:
19 ck12
11:
24 ck12
companding curve
Vsync polarity
Hsync polarity
DAC output range
00:
x1/8
01:
x1/4
10:
x1/2
11:
x1
offset value for ABC
Threshold_1 divided by 4 for defect compensation
Threshold_2 divided by 4 for defect compensation
0:
Defect compensation disable
1:
Defect compensation enable
ABC enable high
Line based digital calibration enable high
Frame based digital calibration enable high
Number of pixels for Frame based digital calibration
00:
4 pixels
01:
8 pixels
10:
16 pixels
11:
32 pixels
Digital timing(column address, CDS timing) disable
Reg_41[0]
flag
R/W
0
Reg_42[2]
Reg_42[1]
Reg_42[0]
Reg_43[7]
Reg_43[6:5]
Reg_43[4:2]
Reg_43[1]
Reg_43[0]
Reg_44[7:6]
mode_chg_ena
dac_pg_lag
fast_i2c
sfrst_ena
shr_ext[1:0]
comp_crv[2:0]
Vsync_p
Hsync_p
dacor[1:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
0
0
0
1
0
0
0
0
1
25
13
0
0
0
0
1
0
Reg_44[5:0]
offset[5:0]
Reg_45[7:0] Threshold_1_by4[7:0]
Reg_46[7:0] Threshold_2_by4[7:0]
Reg_47[5]
Reg_47[4]
Reg_47[3]
Reg_47[2]
Defect_EnH
ABC_EnH
Line_Avg_EnH
Frm_Avg_EnH
Reg_47[1:0] Avg_num_index[1:0]
Reg_48[6]
DSC_pd
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
PixArt Imaging Inc.
E-mail:
fae_service@pixart.com.tw