Philips Semiconductors
Product specification
LIN transceiver
TJA1020
SYMBOL
t
f(slope)(norm)(dom)
PARAMETER
CONDITIONS
MIN.
TYP.
12
MAX.
22.5
UNIT
µs
normal slope fall time LIN normal slope mode;
−
(100% to 0%)
C
L
= 6.8 nF; R
L
= 660
Ω;
V
BAT
= 12 V; transition
from recessive to
dominant; note 4
normal slope rise time
LIN (0% to 100%)
−
normal slope mode;
C
L
= 6.8 nF; R
L
= 660
Ω;
V
BAT
= 12 V; transition
from dominant to
recessive; note 5
normal slope mode;
−4
C
L
= 6.8 nF; R
L
= 660
Ω;
V
BAT
= 12 V;
t
f(slope)(dom)
−
t
r(slope)(rec)
low slope mode;
C
L
= 10 nF; R
L
= 500
Ω;
V
BAT
= 12 V; note 4
low slope mode;
C
L
= 10 nF; R
L
= 500
Ω;
V
BAT
= 12 V; note 5
sleep mode
sleep mode
−
t
r(slope)(norm)(rec)
12
22.5
µs
∆t
slope(norm)
normal slope symmetry
0
+4
µs
t
f(slope)(low)(dom)
low slope fall time LIN
(100% to 0%)
low slope rise time LIN
(0% to 100%)
dominant time for
wake-up via bus
dominant time for
wake-up via pin NWAKE
time period for mode
change from sleep or
standby mode into
normal/low slope mode
time period for mode
change from normal/low
slope mode into sleep
mode
TXD dominant time out
30
62
µs
t
r(slope)(low)(rec)
−
30
62
µs
t
BUS
t
NWAKE
t
gotonorm
30
7
2
70
20
5
150
50
10
µs
µs
µs
t
gotosleep
2
5
10
µs
t
dom
Notes
V
TXD
= 0 V
6
12
20
ms
1. All parameters are guaranteed over the virtual junction temperature by design, but only 100% tested at 125
°C
ambient temperature for dies on wafer level and above this for cased products 100% tested at 25
°C
ambient
temperature, unless otherwise specified.
2. For bare die, all parameters are only guaranteed if the backside of the bare die is connected to ground.
3. If V
BAT
is higher than 12 V, the battery current increases due to the internal LIN termination resistor. The minimum
V
BAT
–
12 V
value of this resistor is 20 kΩ. The maximum current increase is therefore: I
BAT
(
increase
)
=
-------------------------------
-
20 kΩ
4.
( (
t
VLIN
=
40%
)
–
(
t
VLIN
=
95%
) )
t
f(slope)(dom)
=
------------------------------------------------------------------------------------ ; see Fig.6
-
0.55
( (
t
VLIN
=
60%
)
–
(
t
VLIN
=
5%
) )
t
r(slope)(rec)
=
--------------------------------------------------------------------------------- ; see Fig.6
0.55
13
5.
2002 Jul 17
PHILIPS [ NXP SEMICONDUCTORS ]
