Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for
PC monitors
TDA4856
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
BSENS DISCHARGE CIRCUIT: PIN BSENS
VSTOP(BSENS)
discharge stop level
capacitive load;
0.85
1.0
1.15
V
IBSENS = 0.5 mA
VBSENS > 2.5 V
fault condition
Idch(BSENS)
discharge current
4.5
1.2
2
6.0
1.3
−
7.5
1.4
−
mA
V
Vth(BSENS)(restart)
CBSENS(min)
threshold voltage for restart
minimum value of capacitor at
BSENS (pin 4)
nF
Internal reference, supply voltage, soft start and protection
VCC(stab)
external supply voltage for
complete stabilization of all
internal references
9.2
−
16
V
ICC
supply current
−
−
70
9
−
−
mA
mA
ICC(stb)
standby supply current
STDBY = 1; VPLL2 < 1 V;
3.5 V < VCC < 16 V
PSRR
power supply rejection ratio of f = 1 kHz
internal supply voltage
50
−
−
dB
V
VCC(blank)
supply voltage level for
activation of continuous
blanking
VCC decreasing from 12 V 8.2
8.6
9.0
VCC(blank)(min)
minimum supply voltage level
for function of continuous
blanking
V
CC decreasing from 12 V 2.5
3.5
8.3
4.0
8.7
V
V
Von(VCC)
supply voltage level for
activation of HDRV, BDRV,
VOUT1, VOUT2 and
HUNLOCK
VCC increasing from below 7.9
typical 8.1 V
Voff(VCC)
supply voltage level for
VCC decreasing from
7.7
8.1
8.5
V
deactivation of BDRV, VOUT1, above typical 8.3 V
VOUT2 and HUNLOCK; also
sets register SOFTST
THRESHOLDS DERIVED FROM HPLL2 VOLTAGE
VHPLL2(blank)(ul)
VHPLL2(bduty)(ul)
VHPLL2(bduty)(ll)
VHPLL2(hduty)(ul)
VHPLL2(hduty)(ll)
VHPLL2(stb)(ul)
upper limit voltage for
continuous blanking
−
−
−
−
−
−
4.6
4.0
3.2
3.2
1.8
1
−
−
−
−
−
−
V
V
V
V
V
V
upper limit voltage for variation
of BDRV duty cycle
lower limit voltage for variation
of BDRV duty cycle
upper limit voltage for variation
of HDRV duty cycle
lower limit voltage for variation
of HDRV duty cycle
upper limit voltage for standby
voltage
1999 Jul 13
25
NXP [ NXP ]
