Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for
PC monitors
TDA4841PS
Table 3 Activation of protection mode
Power dip recognition
In standby mode the I2C-bus will only answer with an
acknowledge when data is sent to the control register 1AH.
This register contains the standby and soft start control bit.
ACTIVATION
RESET
Low supply voltage at
pin 10
increase supply voltage,
reload registers,
soft start via I2C-bus
If the I2C-bus master transmits data to another register, an
acknowledge is given after the chip address and the
subaddress; an acknowledge is not given after the data.
This indicates that data can be stored into normal registers
only in soft start mode.
Power dip, below 8.1 V
reload registers,
soft start via I2C-bus or via
supply voltage
X-ray protection XRAY
(pin 2) triggered
reload registers,
soft start via I2C-bus
If the supply voltage drops below 8.1 V the deflection
controller leaves normal operation and changes to standby
mode. The microcontroller can check this state by sending
data into a register with the subaddress 0XH.
The acknowledge will only be given on the data if the IC is
active.
HPLL2 (pin 30) externally release pin 30
pulled to ground
When the protection mode is active, several pins of the
TDA4841PS are forced into a defined state:
Due to this behaviour the start-up of the TDA4841PS is
defined as follows: the first data that is transferred to the
deflection controller must be sent to the control register
with subaddress 1AH. Any other subaddress will not lead
to an acknowledge. This is a limitation in checking the
I2C-busses of the monitor during start-up.
HDRV (horizontal driver output) is floating
BDRV (B+ control driver output) is floating
HUNLOCK (indicates, that the frequency-to-voltage
converter is out of lock) is floating (HIGH via external
pull-up resistor)
CLBL provides a continuous blanking signal
VOUT1 and VOUT2 (vertical outputs) are floating
The capacitor at HPLL2 is discharged.
If the soft start procedure is activated via the I2C-bus, all of
these actions will be performed in a well defined sequence
(see Figs 22 and 23).
1999 Oct 25
13
NXP [ NXP ]
