Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for
PC monitors
TDA4841PS
An internal discharge circuit allows a well defined
discharge of capacitors at BSENS. BDRV is active at a
LOW-level output voltage (see Figs 25 and 26), thus it
requires an external inverting driver stage.
Supply voltage stabilizer, references,
start-up procedures and protection functions
The TDA4841PS provides an internal supply voltage
stabilizer for excellent stabilization of all internal
references. An internal gap reference, especially designed
for low-noise, is the reference for the internal horizontal
and vertical supply voltages. All internal reference currents
and drive current for the vertical output stage are derived
from this voltage via external resistors.
The B+ function block can be used for B+ deflection
modulators in many different ways. Two popular
application combinations are:
• Boost converter in feedback mode (see Fig.25)
In this application the OTA is used as an error amplifier
with a limited output voltage range. The flip-flop will be
set at the rising edge of the signal at HDRV. A reset will
be generated when the voltage at BSENS, taken from
the current sense resistor, exceeds the voltage at BOP.
If either the supply voltage is below 8.3 V or no data from
the I2C-bus has been received after power-up, the internal
soft start and protection functions do not allow any of those
outputs [HDRV, BDRV, VOUT1, VOUT2 and HUNLOCK
(see Fig.22)] to be active.
If no reset is generated within a line period, the rising
edge of the next HDRV pulse forces the flip-flop to reset.
The flip-flop is set immediately after the voltage at
BSENS has dropped below the threshold voltage
For supply voltages below 8.3 V the internal I2C-bus will
not generate an acknowledge and the IC is in standby
mode. This is because the internal protection circuit has
generated a reset signal for the soft start register SOFTST.
Above 8.3 V data is accepted and all registers can be
loaded. If the SOFTST register has received a set from the
I2C-bus, the internal soft start procedure is released, which
activates all outputs which are mentioned above.
VRESTART(BSENS)
.
• Buck converter in feed forward mode (see Fig.26)
This application uses an external RC combination at
BSENS to provide a pulse width which is independent
from the horizontal frequency. The capacitor is charged
via an external resistor and discharged by the internal
discharge circuit. For normal operation the discharge
circuit is activated when the flip-flop is reset by the
internal voltage comparator. The capacitor will now be
discharged with a constant current until the internally
controlled stop level VSTOP(BSENS) is reached. This level
will be maintained until the rising edge of the next HDRV
pulse sets the flip-flop again and disables the discharge
circuit.
If during normal operation the supply voltage has dropped
below 8.1 V, the protection mode is activated and
HUNLOCK (pin 17) changes to the protection status and is
floating. This can be detected by the microprocessor.
This protection mode has been implemented in order to
protect the deflection stages and the picture tube during
start-up, shut-down and fault conditions. This protection
mode can be activated as shown in Table 3.
If no reset is generated within a line period, the rising
edge of the next HDRV pulse automatically starts the
discharge sequence and resets the flip-flop. When the
voltage at BSENS reaches the threshold voltage
VRESTART(BSENS), the discharge circuit will be disabled
automatically and the flip-flop will be set immediately.
This behaviour allows a definition of the maximum duty
cycle of the B+ control drive pulse by the relationship of
charge current to discharge current.
1999 Oct 25
12
NXP [ NXP ]
