Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
6
PINNING
Pin description for QFP160
SYMBOL
D1_A0
PIN
1
STATUS
I/O
I/O
I/O
I/O
P
DESCRIPTION
bidirectional digital CCIR 656 D1 port A bit 0
D1_A1
D1_A2
D1_A3
VDDD1
VSSD1
D1_A4
D1_A5
D1_A6
D1_A7
VS_A
2
bidirectional digital CCIR 656 D1 port A bit 1
bidirectional digital CCIR 656 D1 port A bit 2
bidirectional digital CCIR 656 D1 port A bit 3
digital supply voltage 1 (3.3 V)
3
4
5
6
P
digital ground 1
7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P
bidirectional digital CCIR 656 D1 port A bit 4
bidirectional digital CCIR 656 D1 port A bit 5
bidirectional digital CCIR 656 D1 port A bit 6
bidirectional digital CCIR 656 D1 port A bit 7
bidirectional vertical sync signal port A
bidirectional horizontal sync signal port A
bidirectional line-locked system clock port A
8
9
10
11
12
13
14
15
16
17
18
HS_A
LLC_A
PXQ_A
VDDD2
VSSD2
TRST
TMS
bidirectional pixel qualifier signal to mark valid pixels port A; note 1
digital supply voltage 2 (3.3 V)
P
digital ground 2
I
test reset input (JTAG pin must be set LOW for normal operation)
I
test mode select input (JTAG pin must be floating or set to HIGH during normal
operation)
TCLK
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
I
O
I
test clock input (JTAG pin should be set LOW during normal operation)
test data output (JTAG pin not active during normal operation)
test data input (JTAG pin must be floating or set to HIGH during normal operation)
digital supply voltage 3 (3.3 V)
TDO
TDI
VDDD3
P
VSSD3
P
digital ground 3
INTA#
RST
O
I
PCI interrupt line output (active LOW)
PCI global reset input (active LOW)
CLK
I
PCI clock input
GNT#
I
bus grant input signal, PCI arbitration signal (active LOW)
bus request output signal, PCI arbitration signal (active LOW)
digital supply voltage 4 (3.3 V)
REQ#
VDDD4
O
P
VSSD4
P
digital ground 4
AD PCI31
AD PCI30
AD PCI29
AD PCI28
VDDD5
I/O
I/O
I/O
I/O
P
bidirectional PCI multiplexed address/data bit 31
bidirectional PCI multiplexed address/data bit 30
bidirectional PCI multiplexed address/data bit 29
bidirectional PCI multiplexed address/data bit 28
digital supply voltage 5 (3.3 V)
VSSD5
P
digital ground 5
AD PCI27
I/O
bidirectional PCI multiplexed address/data bit 27
1998 Apr 09
6
NXP [ NXP ]
