Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
1
FEATURES
1.1
Video processing
• Full size, full speed video delivery to and from the frame
buffer or virtual system memory enables various
processing possibilities for any external PCI device
• Full bandwidth PCI-bus master write and read (up to
132 Mbytes/s)
1.3
Scaling
• Scaling of video pictures down to randomly sized
windows (vertical down to 1 : 1024; horizontal down to
1 : 256)
• Virtual memory support (4 Mbytes per DMA channel)
• Processing of maximum 4095 active samples per line
and maximum 4095 lines per frame
• High Performance Scaler (HPS) offers two-dimensional,
phase correct data processing for improved signal
quality of scaled video data, especially for compression
applications
• Vanity picture (mirror) for video phone and video
conferencing applications
• Video flip (upside down picture)
• Horizontal and vertical FIR filters with up to 65 taps
• Colour space conversion with gamma correction for
different kinds of displays
• Horizontal upscaling (zoom) supports e.g. CCIR to
square pixel conversion
• Chroma Key generation and utilization
• Additional Binary Ratio Scaler (BRS) supports CIF and
QCIF formats, especially for video phone and video
conferencing.
• Pixel dithering for low resolution video output formats
• Brightness, contrast and saturation control
• Video and Vertical Blanking Interval (VBI) synchronized
programming of internal registers with Register
Programming Sequencer (RPS), ability to control two
asynchronous data streams simultaneously
1.4
Interfacing
• Dual D1 (8-bit, CCIR 656) video I/O interface
• DMSD2 compatible (16-bit YUV) video input interface
• Memory Management Unit (MMU) supports virtual
demand paging memory management (Windows, Unix,
etc.)
• Supports various packed (pixel dithering) and planar
video output formats
• Rectangular clipping of frame buffer areas minimizes
PCI-bus load
• Data Expansion Bus Interface (DEBI) for interfacing with
e.g. MPEG or JPEG decoders with Intel (ISA like) and
Motorola (68000 like) protocol style, capability for
immediate and block mode (DMA) transfers with up to
23 Mbytes/s peak data rate
• Random shape mask clipping protects selectable areas
of frame buffer
• 3 × 128 Dword video FIFO with overflow detection and
‘graceful’ recovery.
• 5 digital audio I/O ports
• 4 independent user configurable General Purpose I/O
1.2
Audio processing
Ports (GPI/O) for interrupt and status processing
• PCI interface (release 2.1)
• I2C-bus interface (bus master).
• Time Slot List (TSL) processing for flexible control of
audio frames up to 256 bits on 2 asynchronous
bidirectional digital audio interfaces simultaneously
(4 DMA channels)
• Video synchronous audio capture, e.g. for sound cards
• Various synchronization modes to support I2S and other
different audio and DSP data formats
• Audio input level monitoring enables peak control via
software
• Programmable bit clock generation for master and slave
applications.
1998 Apr 09
3
NXP [ NXP ]
