Philips Semiconductors
Product specification
Digital video encoder
7
FUNCTIONAL DESCRIPTION
SAA7128H; SAA7129H
Wide screen signalling data can be loaded via the I
2
C-bus
and is inserted into line 23 for standards using 50 Hz field
rate.
VPS data for program dependent automatic start and stop
of such featured VCR’s is loadable via I
2
C-bus.
The IC also contains closed caption and extended data
services encoding (line 21), and supports anti-taping
signal generation in accordance with macrovision. It is also
possible to load data for copy generation management
system into line 20 of every field (525/60 line counting).
A number of possibilities are provided for setting different
video parameters such as:
•
Black and blanking level control
•
Colour subcarrier frequency
•
Variable burst amplitude etc.
During reset (RESET = LOW) and after reset is released,
all digital I/O stages are set to input mode and the encoder
is set to PAL mode and outputs a ‘black burst’ signal on
CVBS and S-video outputs, while RGB outputs are set to
their lowest output voltages. A reset forces the I
2
C-bus
interface to abort any running bus transfer.
7.1
Versatile fader
The digital video encoder encodes digital luminance and
colour difference signals into analog CVBS, S-video and
simultaneously RGB or C
R
-Y-C
B
signals. NTSC-M, PAL
B/G, SECAM and sub-standards are supported.
Both interlaced and non-interlaced operation is possible
for all standards.
The basic encoder function consists of subcarrier
generation and colour modulation and insertion of
synchronization signals. Luminance and chrominance
signals are filtered in accordance with the standard
requirements of
“RS-170-A”
and
“ITU-R BT.470-3”.
For ease of analog post filtering the signals are twice
oversampled with respect to the pixel clock before
digital-to-analog conversion.
The total filter transfer characteristics are illustrated in
Figs 8 to 13. The DACs for Y, C and CVBS are realized
with full 10-bit resolution; 9-bit resolution for RGB output.
The C
R
-Y-C
B
to RGB dematrix can be bypassed optionally
in order to provide the upsampled C
R
-Y-C
B
input signals.
The 8-bit multiplexed C
B
-Y-C
R
formats are
“ITU-R BT.656”
(D1 format) compatible, but the SAV and EAV codes can
be decoded optionally, when the device is operated in
slave mode. Two independent data streams can be
processed, one latched by the rising edge of LLC1, the
other latched by the falling edge of LLC1. The purpose of
that is e.g. to forward one of the data streams containing
both video and On-Screen Display (OSD) information to
the RGB outputs, and the other stream containing video
only to the encoded outputs CVBS and S-video.
For optimum display of RGB signals through a
euro-connector TV set, optionally on the CVBS output an
early composite sync pulse (up to 31 LLC1 clock periods)
can be provided.
As a further alternative, the VBS and C outputs may
provide a second and third CVBS signal.
It is also possible to connect a Philips digital video decoder
(SAA7111, SAA7711A, SAA7112 or SAA7151B) to the
SAA7128H; SAA7129H. Via the RTCI pin, connected to
RTCO of a decoder, information concerning actual
subcarrier, PAL-ID and (with SAA7111 and newer types)
definite subcarrier phase can be inserted.
The device synthesizes all necessary internal signals,
colour subcarrier frequency, and synchronization signals,
from that clock.
Important note:
whenever the fader is activated with the
SYMP bit set to a logic 1 (enabling the detection of
embedded Start of Active Video (SAV) and End of Active
Video (EAV)), codes 00H and FFH are not allowed within
the actual video data (as prescribed by
“ITU-R BT.656”,
anyway). If SAV (00H) has been detected, the fader
automatically passes 100% of the respective signal until
SAV will be detected.
Within the digital video encoder, two data streams can be
faded against each other; these data streams can be input
to the double speed MPEG port, which is able to separate
two independent 27 MHz data streams MP
A
and MP
B
via
a cross switch controlled by EDGE1 and EDGE2.
handbook, halfpage
MPpos
EDGE1 = 0
MPA
E
E
DG
1=
1
ED
GE
MPneg
EDGE2 = 1
2=
0
MPB
MHB574
Fig.3 Cross switch.
2000 Mar 08
8
PHILIPS [ NXP SEMICONDUCTORS ]
