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2000 Mar 08
RESET SDA
40
VDD(I2C)
SA
20
21
I
2
C-BUS
INTERFACE
42
SCL
41
35
5
Philips Semiconductors
Digital video encoder
BLOCK DIAGRAM
XTALI XTALO RCV1 RCV2 TTXRQ XCLK
34
7
8
43
37
LLC1
4
VDDA1 VDDA3
VDDA2 VDDA4
25
28
31
36
SAA7128H
SAA7129H
clock and timing
I
2
C-bus control
SYNC/CLOCK
I
2
C-bus control
I
2
C-bus control
I
2
C-bus control
30
D
OUTPUT
INTERFACE
A
27
24
22
CVBS
(CSYNC)
VBS
(CVBS)
C
(CVBS)
VSSA1
VSSA2
VSSA3
RED
GREEN
BLUE
MP7 to MP0
9 to 16 MPpos
SWITCH
MPneg
MPA
MP
FADER
Y
ENCODER
CbCr
Y
MPB
VP
C
5
I
2
C-bus
TTX
44
control
I
2
C-bus
control
Y
RGB
PROCESSOR
CbCr
A
32
I
2
C-bus control
33
23
26
29
D
5
18
38
6
17
39
2
3
19
MHB572
SAA7128H; SAA7129H
VSSD1 VSSD2 VSSD3 VDDD1 VDDD2 VDDD3
SP
AP
RTCI
Product specification
Fig.1 Block diagram.