Philips Semiconductors
Product specification
Digital video encoder
7.7
Synchronization
SAA7128H; SAA7129H
In slave mode, the horizontal trigger phase can be
programmed to any point in the line, the vertical phase
from line 0 to line 15 counted from the first serration pulse
in half line steps.
Whenever synchronization information cannot be derived
directly from the inputs, the SAA7128H; SAA7129H will
calculate it from the internal horizontal, vertical and PAL
phase. This gives good flexibility with respect to external
synchronization but the circuit does not suppress illegal
settings. In such an event, e.g the odd/even information
may vanish as it does in the non-interlaced modes.
In master mode, the line lengths are fixed to 1728 clocks
at 50 Hz and 1716 clocks at 60 Hz. To allow
non-interlaced frames, the field lengths can be varied by
±0.5
lines. In the event of non-interlace, the SAA7128H;
SAA7129H does not provide odd/even information and the
output signal does not contain the PAL ‘Bruch sequence’.
At the RCV1 pin the IC can provide:
•
A Vertical Sync (VS) signal with 2.5 (50 Hz) or 3 (60 Hz)
lines duration
•
An odd/even signal which is LOW in odd fields
•
A Field Sequence (FSEQ) signal which is HIGH in the
first field of the 4, 8 respectively 12 field sequence.
At the RCV2 pin, there is a horizontal pulse of
programmable phase and duration available. This pulse
can be suppressed in the programmable inactive part of a
field giving a composite blank signal.
The directions and polarities of the RCV ports can be
chosen independently. Timing references can be found in
Tables 52 and 60.
7.8
Clock
The synchronization of the SAA7128H; SAA7129H is able
to operate in two modes; slave mode and master mode.
In master mode (see Fig.19), the circuit generates all
necessary timings in the video signal itself, and it can
provide timing signals at the RCV1 and RCV2 ports.
In slave mode, it accepts timing information either from the
RCV pins or from the embedded timing data of the
ITU-R BT.656 data stream.
For the SAA7128H; SAA7129H, the only difference
between master and slave mode is that it ignores the
timing information at its inputs in master mode. Thus, if in
slave mode, any timing information is missing, the IC will
continue running free without a visible effect. But there
must not be any additional pulses (with wrong phase)
because the circuit will not ignore them.
In slave mode (see Fig.18), an interface circuit decides,
which signal is expected at the RCV1 port and which
information is taken from its active slope. The polarity can
be chosen, if PRCV1 is logic 0 the rising slope will be
active.
The signal can be:
•
A Vertical Sync (VS) pulse; the active slope sets the
vertical phase
•
An odd/even signal; the active slope sets the vertical
phase, the internal field flag to odd and optionally sets
the horizontal phase
•
A Field Sequence (FSEQ) signal; it marks the first field
of the 4 (NTSC), 8 (PAL) respectively 12 (SECAM) field
sequence. In addition to the odd/even signal, it also sets
the PAL phase and optionally defines the subcarrier
phase.
On the RCV2 port, the IC can provide a horizontal pulse
with programmable start and stop phase; this pulse can be
inhibited in the vertical blanking period to build up, for
example, a composite blanking signal.
The horizontal phase can be set via a separate input
RCV2. In the event of VS pulses at RCV1, this is
mandatory. It is also possible to set the signal path to blank
via this input.
From the ITU-R BT.656 data stream, the SAA7128H;
SAA7129H decodes only the start of the first line in the odd
field. All other information is ignored and may miss. If this
kind of slave mode is active, the RCV pins may be
switched to output mode.
The input to LLC1 can either be an external clock source
or the buffered on-chip clock XCLK. The internal crystal
oscillator can be run with either a 3rd-harmonic or a
fundamental crystal.
7.9
I
2
C-bus interface
The I
2
C-bus interface is a standard slave transceiver,
supporting 7-bit slave addresses and 400 kbits/s
guaranteed transfer rate. It uses 8-bit subaddressing with
an auto-increment function. All registers are write and
readable, except one read only status byte.
The I
2
C-bus slave address is defined as 88H with pin 21
(SA) tied LOW and as 8CH with pin 21 (SA) tied HIGH.
2000 Mar 08
12
PHILIPS [ NXP SEMICONDUCTORS ]
