Philips Semiconductors
Preliminary specification
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler
SAA7114H
SYMBOL
C0
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
pF
parallel capacitance
−
3.5 ±20%
−
Clock input timing (XCLK)
Tcy
δ
cycle time
31
40
−
−
45
60
5
ns
%
duty factors for tLLCH/tLLC
rise time
50
−
tr
ns
ns
tf
fall time
−
−
5
Data and control signal input timing X-port, related to XCLK input
tSU;DAT
tHD;DAT
input data set-up time
input data hold time
−
−
10
3
−
−
ns
ns
Clock output timing
CL
Tcy
δ
output load capacitance
15
35
35
−
−
−
50
39
65
pF
ns
%
cycle time
duty factors for
tXCLKH/tXCLKL
tr
tf
rise time
fall time
0.6 to 2.6 V
2.6 to 0.6 V
−
−
−
−
5
5
ns
ns
Data and control signal output timing X-port, related to XCLK output (for XPCK[1:0]83H[5:4] = 00 is default);
note 2
CL
output load capacitance
output data hold time
15
−
−
50
−
pF
ns
ns
tOHD;DAT
tPD
CL = 15 pF
CL = 15 pF
14
24
propagation delay from
positive edge of XCLK
output
−
−
tf
fall time
−
−
<tbf>
ns
Control signal output timing RT port, related to LLC output
CL
output load capacitance
output hold time
15
−
−
50
−
pF
ns
ns
tOHD;DAT
tPD
CL = 15 pF
CL = 15 pF
14
24
propagation delay from
positive edge of LLC
output
−
−
tf
fall time
−
−
<tbf>
ns
ICLK output timing
CL
Tcy
δ
output load capacitance
15
31
35
−
−
−
−
−
50
45
65
5
pF
ns
%
cycle time
duty factors for tICLKH/tICLKL
rise time
tr
0.6 to 2.6 V
ns
2000 Mar 15
76
NXP [ NXP ]
