Philips Semiconductors
Preliminary specification
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler
SAA7114H
SYMBOL
LEdc(d)
PARAMETER
CONDITIONS
MIN.
TYP.
0.7
MAX.
UNIT
DC differential linearity
error
−
−
−
−
LSB
LEdc(i)
DC integral linearity error
1
LSB
Digital inputs
VIL(SCL,SDA)
LOW-level input voltage
pins SDA and SCL
−0.5
0.7VDDD
−0.3
2.0
−
−
−
−
−
−
+0.3VDDD
VDDD + 0.5
+0.8
V
V
V
V
V
V
VIH(SCL,SDA)
VIL(XTALI)
VIH(XTALI)
VIL(n)
HIGH-level input voltage
pins SDA and SCL
LOW-level CMOS input
voltage pin XTALI
HIGH-level CMOS input
voltage pin XTALI
VDDD + 0.3
+0.8
LOW-level input voltage all
other inputs
−0.3
2.0
VIH(n)
HIGH-level input voltage
all other inputs
5.5
ILI
input leakage current
I/O leakage current
input capacitance
−
−
−
−
−
−
1
µA
µA
pF
ILI/O
Ci
10
8
I/O at high impedance
Digital outputs; note 1
VOL(SDA)
VOL(clk)
VOH(clk)
VOL
LOW-level output voltage
pin SDA
SDA at 3 mA sink current
−
−
−
−
−
−
0.4
V
V
V
V
V
LOW-level output voltage
for clocks
−0.5
2.4
0
+0.6
HIGH-level output voltage
for clocks
VDDD + 0.5
0.4
LOW-level output voltage
all other digital outputs
VOH
HIGH-level output voltage
all other digital outputs
2.4
VDDD + 0.5
Clock output timing (LLC and LLC2); note 2
CL
output load capacitance
cycle time
15
35
70
40
−
−
−
−
50
39
78
60
pF
ns
ns
%
Tcy
pin LLC
pin LLC2
CL = 40 pF
δ
duty factors for tLLCH/tLLC
and tLLC2H/tLLC2
tr
rise time LLC and LLC2
fall time LLC and LLC2
0.2 V to VDDD − 0.2 V
−
−
−
−
5
ns
ns
ns
tf
VDDD − 0.2 V to 0.2 V
−
5
td(LLC-LLC2)
delay time between LLC
and LLC2 output
measured at 1.5 V;
CL = 25 pF
−4
+8
2000 Mar 15
74
NXP [ NXP ]
