Philips Semiconductors
Preliminary specification
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler
SAA7114H
• VBI-raw sample streams are enveloped with
SAV and EAV, like normal video
There are no empty cycles in the ancillary code and its
data field. The data codes 00H and FFH are suppressed
(changed to 01H or FEH respectively) in active video
stream, as well as in VBI-raw sample stream (VBI
pass-through). Optionally the number range can be limited
further.
• Decoded VBI-data is transported as Ancillary (ANC)
data, two modes:
– direct decoded VBI-data bytes (8-bit) are directly
placed in the ANC data field, 00H and FFH codes
may appear in data block (violation to CCIR-656)
– recoded VBI-data bytes (8-bit) directly placed in ANC
data field, 00H and FFH codes will be recoded to
even parity codes 03H and FCH to suppress invalid
CCIR-656 codes.
Table 31 Signals dedicated to the image port
SYMBOL
PIN
I/O
DESCRIPTION
BIT
IPD7 to
IPD0
54 to 57 I/O I-port data
and
ICODE[93H[7]], ISWP[1:0]85H[7:6]
and IPE[1:0]87[1:0]
59 to 62
ICLK
IDQ
45
46
53
52
I/O continuous reference clock at image port, can
be input or output, as output decoder LLC or
XCLK from X-port
ICKS[1:0]80H[1:0] and
IPE[1:0]87H[1:0]
O
O
O
data valid flag at image port, qualifier, with
programmable polarity;
secondary function: gated clock
ICKS2[80H[2]], IDQP[85H[0]] and
IPE[1:0]87H[1:0]
IGPH
IGPV
horizontal reference output signal, copy of the
H-gate signal of the scaler, with programmable IPE[1:0]87H[1:0]
polarity; alternative functions: HRESET pulse
IDH[1:0]84H[1:0], IRHP[85H[1]] and
vertical reference output signal, copy of the
V-gate signal of the scaler, with programmable
polarity;
IDV[1:0]84H[3:2], IRVP[85H[2]] and
IPE[1:0]87H[1:0]
alternative functions: VRESET pulse
IGP1
IGP0
49
48
O
O
general purpose output signal for I-port
IDG12[86H[4]], IDG1[1:0]84H[5:4],
IG1P[85H[3]] and IPE[1:0]87H[1:0]
general purpose output signal for I-port
IDG02[86H[5]], IDG0[1:0]84H[7:6],
IG0P[85H[4]] and IPE[1:0]87H[1:0]
ITRDY
ITRI
42
47
I
I
target ready input signals
−
port control, switches I-port into 3-state
IPE[1:0]87H[1:0]
2000 Mar 15
66
NXP [ NXP ]
