Philips Semiconductors
Preliminary specification
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler
SAA7114H
9.6
Host port for 16-bit extension of video data I/O (H-port)
The H-port pins HPD can be used for extension of the data I/O paths to 16-bit.
Functional priority has the I-port. If I8_16[93H[6]] is set to logic 1 the output drivers of the H-port are enabled dependent
on the I-port enable control. For I8_16 = 0, the HPD output is disabled.
Table 32 Signals dedicated to the host port
SYMBOL
PIN
I/O
DESCRIPTION
BIT
HPD7 to HPD0 64 to 67 I/O 16-bit extension for digital I/O (chrominance
IPE[1:0]87H[1:0], ITRI[8FH[6]] and
I8_16[93H[6]]
and
component)
69 to 72
9.7
Basic input and output timing diagrams I-port and X-port
9.7.1
I-PORT OUTPUT TIMING
The following diagrams are sketching the output timing via the I-port. IGPH and IGPV are sketched as logic 1 active gate
signals. If reference pulses are programmed, these pulses are generated on the rising edge of the logic 1 active gates.
Valid data is accompanied by the output data qualifier on pin IDQ. In addition invalid cycles are marked with output code
00H.
The IDQ output pin may be defined to be a gated clock output signal (ICLK AND internal IDQ).
9.7.2
X-PORT INPUT TIMING
At the X-port the input timing requirements are the same as sketched for the I-port output. But different to this:
• It is not necessary to mark invalid cycles with a 00H code
• No constraints on the input qualifier (can be a random pattern)
• XCLK may be a gated clock (XCLK AND external XDQ).
Remark: All timings illustrated in Figs 31 to 37 are given for an uninterrupted output stream (no handshake with the
external hardware).
handbook, full pagewidth
ICLK
IDQ
[
]
C
B
C
C
C
R
IPD 7:0
00
FF
00
00
SAV
00
Y
Y
00
Y
Y
00
R
B
IGPH
MHB550
Fig.31 Output timing I-port for serial 8-bit data at start of a line (ICODE = 1).
2000 Mar 15
67
NXP [ NXP ]
