Philips Semiconductors
Preliminary specification
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler
SAA7114H
9
INPUT/OUTPUT INTERFACES AND PORTS
9.1
Analog terminals
The SAA7114H has 5 different I/O interfaces:
The SAA7114H has 6 analog inputs AI21 to AI24, AI11
and AI12 for composite video CVBS or S-video Y/C signal
pairs. Additionally, there are two differential reference
inputs, which must be connected to ground via a capacitor
equivalent to the decoupling capacitors at the 6 inputs.
There are no peripheral components required other than
these decoupling capacitors and 18 Ω/56 Ω termination
resistors, one set per connected input signal (see also
application example in Fig.40). Two anti-alias filters are
integrated, and self adjusting via the clock frequency.
• Analog video input interface, for analog CVBS and/or
Y and C input signals
• Audio clock port
• Digital real-time signal port (RT port)
• Digital video expansion port (X-port), for unscaled digital
video input and output
• Digital image port (I-port) for scaled video data output
and programming
Clamp and gain control for the two ADC’s are also
integrated. An analog video output pin AOUT is provided
for testing purposes.
• Digital host port (H-port) for extension of the image port
or expansion port from 8 to 16-bit.
Table 23 Analog pin description
SYMBOL
AI24 to AI21
AI12 and AI11
AOUT
PIN
10, 12, 14 and 16
18 and 20
22
I/O
DESCRIPTION
BIT
I
analog video signal inputs, e.g. 2 CVBS signals and
two Y/C pairs can be connected simultaneously
MODE3 to MODE0
O
I
analog video output, for test purposes
AOSL1 and AOSL0
AI1D and AI2D
19 and 13
analog reference pins for differential ADC operation
−
9.2
Audio clock signals
An audio master clock AMCLK and two divided clocks
ASCLK and ALRCLK are generated;
The SAA7114H also synchronizes the audio clock and
sampling rate to the video frame rate, via a very slow PLL.
This ensures that the multimedia capture and compression
processes always gather the same predefined number of
samples per video frame.
•
ASCLK: can be used as audio serial clock
• ALRCLK: audio left/right channel clock.
The ratios are programmable, see also Section 8.6.
Table 24 Audio clock pin description
SYMBOL PIN I/O
DESCRIPTION
audio master clock output
BIT
AMCLK
37
O
ACPF[17:0]32H[1:0]31H[7:0]30H[7:0] and
ACNI[21:0]36H[5:0]35H[7:0]34H[7:0]
AMXCLK 41
I
external audio master clock input for the clock
division circuit, can be directly connected to output
AMCLK for standard applications
−
ASCLK
39
40
O
O
serial audio clock output, can be synchronized to
rising or falling edge of AMXCLK
SDIV[5:0]38H[5:0] and SCPH[3AH[0]]
LRDIV[5:0]39H[5:0] and LRPH[3AH[1]]
ALRCLK
audio channel (left/right) clock output, can be
synchronized to rising or falling edge of ASCLK
2000 Mar 15
60
NXP [ NXP ]
