Philips Semiconductors
Preliminary specification
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler
SAA7114H
8.6.2
SIGNALS ASCLK AND ALRCLK
• LRDIV[5:0]39H[5:0] according to the equation:
fASCLK
fASCLK
Two binary divided signals ASCLK and ALRCLK are
provided for slower serial digital audio signal transmission
and for channel-select. The frequencies of these signals
are defined by the parameters:
f ALRCLK
=
LRDIV[5:0] =
--------------------------
----------------------
2fALRCLK
LRDIV × 2
See Table 22 for examples.
• SDIV[5:0]38H[5:0] according to the equation:
f
SDIV[5:0] = AMXCLK – 1
fAMXCLK
-------------------
fASCLK
=
-------------------------------------
2fASCLK
(SDIV + 1) × 2
Table 22 Programming examples for ASCLK/ALRCLK clock generation
SDIV
LRDIV
AMXCLK
(MHz)
ASCLK
(kHz)
ALRCLK
(kHz)
DECIMAL
HEX
DECIMAL
HEX
1536
768
3
7
3
1
3
1
03
07
03
01
03
01
16
8
10
08
10
10
10
10
12.288
11.2896
8.192
48
44.1
32
1411.2
2822.4
1024
16
32
16
32
2048
8.6.3
OTHER CONTROL SIGNALS
LRPH[3AH[1]]; ALRCLK Phase
0: invert ASCLK, ALRCLK edges triggered by falling
edge of ASCLK
Further control signals are available to define reference
clock edges and vertical references:
1: don’t invert ASCLK, ALRCLK edges triggered by
rising edge of ASCLK
APLL[3AH[3]]; Audio PLL mode:
0: PLL closed
SCPH[3AH[0]]; ASCLK Phase:
1: PLL open
0: invert AMXCLK, ASCLK edges triggered by falling
edge of AMXCLK
AMVR[3AH[2]]; Audio Master clock Vertical Reference:
0: internal V
1: external V
1: don’t invert AMXCLK, ASCLK edges triggered by
rising edge of AMXCLK
2000 Mar 15
59
NXP [ NXP ]
