Philips Semiconductors
Product specification
9-bit video input processor
SAA7113H
Table 2 Power-on control sequence
INTERNAL POWER-ON
CONTROL SEQUENCE
PIN OUTPUT STATUS
REMARKS
Directly after power-on
asynchronous reset
VPO7 to VPO0, RTCO, RTS0, RTS1,
SDA and LLC are in high-impedance state 20 to 200 ms
direct switching to high-impedance for
Synchronous reset
sequence
LLC and SDA become active;
VPO7 to VPO0, RTCO, RTS0 and RTS1
are held in high-impedance state
internal reset sequence
Status after power-on
control sequence
VPO7 to VPO0, RTCO, RTS0 and RTS1
are held in high-impedance state
after power-on (reset sequence) a complete
I2C-bus transmission is required
Several standards can be selected per VBI line.
The supported VBI data standards are described in
Table 3.
8.8
Multi-standard VBI data slicer
The multi-standard data slicer is a Vertical Blanking
Interval (VBI) and Full Field (FF) video data acquisition
block. In combination with software modules the slicer
acquires most existing formats of broadcast VBI and FF
data.
The programming of the desired standards is done via
I2C-bus subaddresses 41H to 57H
(LCR2[7 : 0] to LCR24[7 : 0]); see detailed description in
Chapter 8.10. To adjust the slicers processing to the
signals source, there are offsets in horizontal and vertical
direction available via the I2C-bus in subaddresses 5BH
(bits 2 to 0), 59H (HOFF10 to HOFF0) and 5BH (bit 4),
5AH (VOFF8 to VOFF0). The formatting of the decoded
VBI data is done within the output interface to the
VPO-bus. For a detailed description of the sliced data
format see Table 17.
The implementation and programming model of the
multi-standard VBI data slicer is similar to the text slicer
built in the “Multimedia Video Data Acquisition Circuit
SAA5284”.
The circuitry recovers the actual clock phase during the
clock-run-in-period, slices the data bits with the selected
data rate, and groups them into bytes. The clock
frequency, signals source, field frequency and accepted
error count must be defined via the I2C-bus in
subaddress 40H, AC1: bits D7 to D4.
Table 3 Supported VBI standards
DATA RATE
(Mbits/s)
FC
WINDOW
HAM
CHECK
STANDARD TYPE
Teletext EuroWST, CCST
FRAMING CODE
6.9375
27H
001
WST625
CC625
VPS
always
European closed caption
VPS
0.500
5
9951H
Wide screen signalling bits
US teletext (WST)
5
1E3C1FH
WSS
5.7272
0.503
6.9375
1.8125
1.7898
5.7272
5.7272
5
27H
WST525
CC525
always
US closed caption (line 21)
Teletext
001
programmable
programmable
programmable
programmable
programmable (A7H)
programmable
general text optional
VITC625
VITC/EBU time codes (Europe)
VITC/SMPTE time codes (USA)
US NABTS
VITC625
NABTS
Japtext
optional
MOJI (Japanese)
Japanese format switch (L20/22)
1999 Jul 01
24
NXP [ NXP ]
