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g
Y
LUM
LUMINANCE CIRCUIT
WEIGHTING
AND
ADDING
STAGE
VARIABLE
BAND-PASS
FILTER
CHROMINANCE
TRAP
PREFILTER
PREF
BYPS
VBLB
BPSS0
BPSS1
PREF
APER0
APER1
VBLB
MATCHING
AMPLIFIER
PREFILTER
SYNC
CLOCK CIRCUIT
CLOCKS
MACROVISION
DETECTOR
COPRO
VBLB
LINE-LOCKED
CLOCK
GENERATOR
17
LLC
V
PHASE
DETECTOR
FINE
SYNC SLICER
PHASE
DETECTOR
COARSE
10
11
40
CLOCK
GENERATION
CIRCUIT
DDA0
V
DAC6
SYNCHRONIZATION CIRCUIT
SSA0
CE
AUFD
VNOI0
VNOI1
HSB (7 : 0)
HSS (7 : 0)
2
I C-BUS CONTROL
HPLL
HTC (1 : 0)
HTC (1 : 0)
HTC (1 : 0)
FIDT
FSEL HLCK
INCS
32
31
DISCRETE
TIME
OSCILLATOR 2
CRYSTAL
CLOCK
GENERATOR
XTALI
XTAL
2
I C-BUS
LOOP FILTER
2
VERTICAL
PROCESSOR
COUNTER
INTERFACE
24 23
26
27
MHB329
RTS0
RTS1
SCL SDA
Fig.19 Luminance and sync processing.
NXP [ NXP ]
