Philips Semiconductors
Product specification
9-bit video input processor
SAA7113H
8.5
Synchronization
8.6
Clock generation circuit
The prefiltered luminance signal is fed to the
The internal CGC generates all clock signals required for
the video input processor. The internal signal LFCO is a
digital-to-analog converted signal provided by the
horizontal PLL. It is the multiple of the line frequency
[6.75 MHz = 429 × fH (50 Hz) or 432 × fH (60 Hz)].
synchronization stage. Its bandwidth is further reduced to
1 MHz in a low-pass filter. The sync pulses are sliced and
fed to the phase detectors where they are compared with
the sub-divided clock frequency. The resulting output
signal is applied to the loop filter to accumulate all phase
deviations. Internal signals (e.g. HCL and HSY) are
generated in accordance with analog front-end
requirements. The loop filter signal drives an oscillator to
generate the line frequency control signal LFCO,
see Fig.19.
Internally the LFCO signal is multiplied by a factor of
2 and 4 in the PLL circuit (including phase detector, loop
filtering, VCO and frequency divider) to obtain the output
clock signals. The rectangular output clocks have a 50%
duty factor.
The detection of ‘pseudo syncs’ as part of the macrovision
copy protection standard is also done within the
synchronization circuit.
The result is reported as flag COPRO within the decoder
status byte at subaddress 1FH.
handbook, full pagewidth
ZERO
BAND PASS
PHASE
DETECTION
LOOP
FILTER
CROSS
LFCO
OSCILLATOR
LLC
FC = LLC/4
DETECTION
DIVIDER
1/2
DIVIDER
1/2
LLC2
MHB330
Fig.20 Block diagram of clock generation circuit.
Table 1 Clock frequencies
8.7
Power-on reset and CE input
A missing clock, insufficient digital or analog VDDA0 supply
voltages (below 2.8 V) will initiate the reset sequence; all
outputs are forced to 3-state (see Fig.21).
CLOCK
FREQUENCY (MHz)
XTAL
24.576
27
LLC
It is possible to force a reset by pulling the Chip Enable
(CE) to ground. After the rising edge of CE and sufficient
power supply voltage, the outputs LLC and SDA return
from 3-state to active, while RTS0, RTS1 and RTCO
remain in 3-state and have to be activated via I2C-bus
programming (see Table 2).
LLC2 (internal)
LLC4 (internal)
LLC8 (virtual)
13.5
6.75
3.375
1999 Jul 01
22
NXP [ NXP ]
