Philips Semiconductors
Product specification
RDS/RBDS pre-processor
SAA6588
Table 4 Selection of error correction mode for synchronization search
SYM1
SYM0
MODE
DESCRIPTION
0
0
1
1
0
1
0
1
SYNCA no error correction
SYNCB error correction of a burst error maximum 2 bits
SYNCC error correction of a burst error maximum 5 bits
SYNCD no error correction; no E-E block sequence allowed (for RBDS mode, E-A or D-E
block sequences are still allowed)
Table 5 Selection of data output protocol and DAVN signal
DAC1
DAC0
MODE
DAVA standard
processing mode synchronization search: DAVN = HIGH;
synchronized: block information available and DAVN active after
FUNCTION
DESCRIPTION
0
0
RDS standard output mode;
detection of a new block (every 26 bits)
0
1
1
1
0
1
DAVB fast PI search
mode
synchronization search: for fast PI search, block information
available and DAVN active only if a correct A-block is detected;
synchronized: same as standard DAVA mode
DAVC reduced data
request
synchronization search: DAVN inactive = HIGH;
synchronized: block information available and DAVN active only
processing mode after detection of two new blocks (every 52 bits)
−
−
−
Table 6 Description of pause level and flywheel setting bytes (byte1W)
BIT
NAME
FUNCTION
7
6
PL1
PL0
level sensitivity for pause detection; see Table 8
5 to 0
FEB5 to FEB0
maximum number of error blocks for synchronization hold flywheel (0 to 63)
Table 7 Description of pause time/oscillator frequency and quality detector sensitivity setting (byte 2W)
BIT
NAME
FUNCTION
7
6
5
PTF1
PTF0
SOSC
time criteria for pause (20 to 160 ms); see Table 9
oscillator frequency: n × 4.332 MHz (n = 1 to 4); see Table 9
0: set pause time criteria via PFT1 and PFT0
1: select oscillator frequency via PFT1 and PFT0
4 to 0
SQS4 to SQS0
adjustment of signal quality detector sensitivity (−9 to +9.6 dB); see Table 10
Table 8 Control bits PL0 and PL1
PAUSE LEVEL
(mV RMS)
BELOW DOLBY LEVEL
(dB)
FM DEVIATION
(kHz)
PL1
PL0
0
0
1
1
0
1
0
1
11
17
27
43
30.2
26.2
22.2
18.2
1.0
1.6
2.5
4.0
1997 Sep 01
12
NXP [ NXP ]
