Philips Semiconductors
Product specification
RDS/RBDS pre-processor
SAA6588
received (every 52 bits), the actual RDS/RBDS
Data processing control
information of the last two blocks is available with every
two new received blocks.
The pre-processor provides different operating modes
selectable via the external I2C-bus. The data processing
control performs the pre-selected operating modes and
controls the requested output of the RDS/RBDS
information.
The RDS/RBDS pre-processor provides data output of the
block identification, the RDS/RBDS information words and
error detection and correction status of the last two blocks
as well as signal quality indication and general decoder
status information.
Restart of synchronization mode:
The ‘restart synchronization’ (NWSY) control mode
immediately terminates the actual synchronization and
restarts a new synchronization search procedure.
The NWSY flag is automatically reset after the restart of
synchronization by the decoder.
In addition, the decoder controls also the data request from
the external main controller. The pre-processor activates
the ‘data overflow’ status flag DOFL
(see Section “Programming”), if the decoder is
synchronized and a new RDS/RBDS block is received
before the previously processed block was completely
transmitted via I2C-bus. After detection of data overflow
the interface registers are not updated until reset of the
data overflow flag by reading via the I2C-bus.
This mode is required for a fast new synchronization on
the RDS/RBDS data from a new transmitter station if the
tuning frequency is changed by the radio set.
Restart of synchronization search is furthermore
automatically carried out if the internal flywheel signals
a loss of synchronization (see Section “Flywheel for
synchronization hold”).
RDS/RBDS data output
The decoded RDS/RBDS block information and the
current pre-processor status is available via the I2C-bus.
For synchronization of data request between main
controller and pre-processor the additional data available
output signal is used.
Error correction control mode for synchronization:
For error correction and identification of valid blocks
during synchronization search, three different modes
are selectable. (SYM1, SYM0, see Table 4).
If the decoder has processed new information for the main
controller the data available signal (DAVN) is activated
(LOW) under the following conditions (see also Table 5):
RBDS processing mode:
The pre-processor is suitable for receivers intended for
the European (RDS) as well as for the USA (RBDS)
standard. If RBDS mode is selected via the I2C-bus, the
block detection and the error detection and correction
are adjusted to RBDS data processing.
• During synchronization search in DAVB mode if a valid
A-block has been detected. This mode can be used for
fast search tuning (detection and comparison of the PI
code contained in the A-block).
Data available control mode:
• During synchronization search in any DAV mode, if two
blocks in correct sequence have been detected
(synchronization criterion).
The pre-processor provides three different RDS/RBDS
data output processing modes selectable via the ‘data
available’ control mode: (see also Section “RDS/RBDS
data output” and Table 5).
• If the pre-processor is synchronized and in mode DAVA
and DAVB a new block has been processed. This mode
is the standard data processing mode, if the decoder is
synchronized.
Standard processing mode: if the decoder is
synchronized and a new block is received (every
26 bits), the actual RDS/RBDS information of the last
two blocks is available with every new received block.
• If the pre-processor is synchronized and in DAVC mode
two new blocks have been processed.
Fast PI search mode: during synchronization search
and if a new A-block is received, the actual RDS/RBDS
information of this or the last two A-blocks respectively
is available with every new received A-block. If the
decoder is synchronized, the standard processing mode
is valid.
• If the pre-processor is synchronized and in any DAV
mode loss of synchronization is detected (flywheel
counter overflow and resulting restart of
synchronization).
• In any DAV mode, if a reset condition caused by
power-on or voltage-drop is detected.
Reduced data request processing mode: if the
decoder is synchronized and two new blocks are
1997 Sep 01
8
NXP [ NXP ]
