PDIUSBD12
USB interface device with parallel bus
Philips Semiconductors
successful transaction. The exception is during DMA operation on the main endpoint
(endpoint 2), in which case the pointer is automatically pointed to the second buffer
after reaching the boundary (double buffering scheme).
11.3.7 Clear buffer
Code (Hex) — F2
Transaction — none
When a packet is received completely, an internal endpoint buffer full flag is set. All
subsequent packets will be refused by returning a NAK. When the microcontroller has
read the data, it should free the buffer by the Clear Buffer command. When the buffer
is cleared, new packets will be accepted.
11.3.8 Validate buffer
Code (Hex) — FA
Transaction — none
When the microprocessor has written data into an IN buffer, it should set the buffer
full flag by the Validate Buffer command. This indicates that the data in the buffer are
valid and can be sent to the host when the next IN token is received.
11.3.9 Set endpoint status
Code (Hex) — 40 to 45
Transaction — write 1 byte
A stalled control endpoint is automatically unstalled when it receives a SETUP token,
regardless of the content of the packet. If the endpoint should stay in its stalled state,
the microcontroller can re-stall it.
When a stalled endpoint is unstalled (either by the Set Endpoint Status command or
by receiving a SETUP token), it is also re-initialized. This flushes the buffer and if it is
an OUT buffer it waits for a DATA 0 PID, if it is an IN buffer it writes a DATA 0 PID.
Even when unstalled, writing Set Endpoint Status to ‘0’ initializes the endpoint.
STALLED: A ‘1’ indicates the endpoint is stalled.
Fig 14. Set endpoint status: bit allocation.
11.3.10 Acknowledge setup
Code (Hex) — F1
Transaction — none
9397 750 09238
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
Product data
Rev. 08 — 20 December 2001
20 of 35
NXP [ NXP ]
