Philips Semiconductors
Product specification
Clock/calendar with 240 × 8-bit RAM
PCF8583
8
CHARACTERISTICS OF THE I2C-BUS
The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a serial data
line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data
transfer may be initiated only when the bus is not busy.
8.1
Bit transfer (see Fig.12)
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period
of the clock pulse as changes in the data line at this time will be interpreted as a control signal.
SDA
SCL
data line
stable;
data valid
change
of data
allowed
MBC621
Fig.12 Bit transfer.
8.2
Start and stop conditions (see Fig.13)
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is
defined as the stop condition (P).
SDA
SCL
SDA
SCL
S
P
STOP condition
START condition
MBC622
Fig.13 Definition of start and stop conditions.
1997 Jul 15
14
NXP [ NXP ]
