PCF8583
NXP Semiconductors
Clock and calendar with 240 x 8-bit RAM
7.3 Control and status register
The control and status register is defined as the memory location 00h with free access for
reading and writing via the I2C-bus. All functions and options are controlled by the
contents of the control and status register (see Figure 5).
MSB
7
LSB
0
memory location 00h
reset state: 0000 0000
6
5
4
3
2
1
timer flag:
50 % duty factor
seconds flag if alarm enable bit
is logic 0
alarm flag: 50 % duty factor
minutes flag if alarm enable bit
is logic 0
alarm enable bit:
logic 0:
alarm disabled: flags toggle
alarm control register to disabled
(memory locations 08h to 0Fh
are free RAM space)
logic 1:
enable alarm control register
(memory location 08h is the
alarm control register)
mask flag:
logic 0:
read locations 05h to 06h
unmasked
logic 1:
read date and month count
directly
function mode:
clock mode 32.768 kHz
clock mode 50 Hz
event-counter mode
test modes
00
01
10
11
hold last count flag:
count
logic 0:
logic 1:
store and hold last count in
capture latches
stop counting flag:
013aaa370
count pulses
stop counting, reset divider
logic 0:
logic 1:
Fig 5. Control and status register
PCF8583
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 — 6 October 2010
6 of 37
NXP [ NXP ]
