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g
SCL
SDA
S
0
1
0
0
A2 A1 A0
1
A
P07 P06 P05 P04 P03 P02 P01 P00
A
P17
P10
A
P07
P00
A
P17
P10
1
P
acknowledge
from receiver
acknowledge
from receiver
non acknowledge
from receiver
R/W acknowledge
from slave
acknowledge
from receiver
READ FROM PORT
DATA INTO PORT
P07 to P00
P17 to P10
P07 to P00
P17 to P10
P07 to P00
P17 to P10
t
t
h
su
INT
MGL543
t
t
t
ir
iv
ir
A LOW-to-HIGH transition of SDA, while SCL is HIGH is defined as the STOP condition (P). Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present
at the latest acknowledge phase is valid (output mode). Input data is lost.
Fig.10 READ mode (input).
NXP [ NXP ]
