Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
5
PINNING
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
LCD backplane outputs
I
2
C-bus slave address bit 0 input
logic ground
LCD supply voltage
A2
9
PCF8566
SYMBOL
SDA
SCL
SYNC
CLK
V
DD
OSC
A0
A1
A2
SA0
V
SS
V
LCD
BP0
BP2
BP1
BP3
DESCRIPTION
I
2
C-bus data input/output
I
2
C-bus
clock input/output
cascade synchronization
input/output
external clock input/output
positive supply voltage
oscillator input
I
2
C-bus
subaddress inputs
handbook, halfpage
SDA
SCL
SYNC
CLK
VDD
OSC
A0
A1
1
2
3
4
5
6
7
8
40 S23
39 S22
38 S21
37 S20
36 S19
35 S18
34 S17
33 S16
32 S15
31 S14
SA0 10
VSS 11
VLCD 12
BP0 13
BP2 14
BP1 15
BP3 16
S0 17
S1 18
S2 19
S3 20
MGG382
PCF8566
30 S13
29 S12
28 S11
27 S10
26 S9
25 S8
24 S7
23 S6
22 S5
21 S4
S0 to S23 17 to 40 LCD segment outputs
Fig.2 Pin configuration.
1998 May 04
5
PHILIPS [ NXP SEMICONDUCTORS ]
