Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
1
FEATURES
PCF8566
•
Single-chip LCD controller/driver
•
Selectable backplane drive configuration: static
or 2, 3 or 4 backplane multiplexing
•
Selectable display bias configuration: static,
1
⁄
2
or
1
⁄
3
•
Internal LCD bias generation with voltage-follower
buffers
•
24 segment drives: up to twelve 8-segment numeric
characters; up to six 15-segment alphanumeric
characters; or any graphics of up to 96 elements
•
24
×
4-bit RAM for display data storage
•
Auto-incremented display data loading across device
subaddress boundaries
•
Display memory bank switching in static and duplex
drive modes
•
Versatile blinking modes
•
LCD and logic supplies may be separated
•
2.5 to 6 V power supply range
•
Low power consumption
•
Power saving mode for extremely low power
consumption in battery-operated and telephone
applications
•
I
2
C-bus interface
•
TTL/CMOS compatible
•
Compatible with any 4-bit, 8-bit or 16-bit
microprocessors/microcontrollers
•
May be cascaded for large LCD applications
(up to 1536 segments possible)
•
Cascadable with the 40 segment LCD driver PCF8576C
•
Optimized pinning for single plane wiring in both single
and multiple PCF8566 applications
•
Space-saving 40 lead plastic very small outline package
(VSO40; SOT158-1)
•
No external components required (even in multiple
device applications)
•
Manufactured in silicon gate CMOS process.
3
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
PCF8566P
PCF8566T
DIP40
VSO40
DESCRIPTION
plastic dual in-line package; 40 leads (600 mil)
plastic very small outline package; 40 leads
VERSION
SOT129-1
SOT158-1
2
GENERAL DESCRIPTION
The PCF8566 is a peripheral device which interfaces to
almost any Liquid Crystal Display (LCD) having low
multiplex rates. It generates the drive signals for any static
or multiplexed LCD containing up to four backplanes and
up to 24 segments and can easily be cascaded for larger
LCD applications. The PCF8566 is compatible with most
microprocessors/microcontrollers and communicates via a
two-line bidirectional I
2
C-bus. Communication overheads
are minimized by a display RAM with auto-incremented
addressing, by hardware subaddressing and by display
memory switching (static and duplex drive modes).
1998 May 04
3
PHILIPS [ NXP SEMICONDUCTORS ]
