PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
V
DD
V
LCD
5
12
SDA
SCL
1
2
24 segment drives
17 to 40
LCD PANEL
SYNC
CLK
PCF8566
3
4
6
(up to 1536
elements)
13 to 16
OSC
BP0 to BP3
(open-circuit)
7
8
9
10 11
A0 A1 A2 SA0 V
SS
V
LCD
V
DD
t
rise
R ≤
2 C
V
V
LCD
bus
DD
5
12
SDA
SCL
HOST
MICRO-
1
24 segment drives
17 to 40
2
3
4
6
PROCESSOR/
MICRO-
CONTROLLER
SYNC
CLK
PCF8566
4 backplanes
BP0 to BP3
13 to 16
OSC
7
8
9
10 11
mgg384
A0 A1 A2 SA0
V
SS
V
SS
Fig 26. Cascaded PCF8566 configuration
The SYNC line is provided to maintain the correct synchronization between all cascaded
PCF8566s. This synchronization is guaranteed after the power-on reset. The only time
that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in
adverse electrical environments or by defining a multiplex mode when PCF8566s with
differing SA0 levels are cascaded).
SYNC is organized as an input/output pin; the output selection being realized as an
open-drain driver with an internal pull-up resistor. A PCF8566 asserts the SYNC line at
the onset of its last active backplane signal and monitors the SYNC line at all other times.
If synchronization in the cascade is lost, it is restored by the first PCF8566 to assert
SYNC. The timing relationship between the backplane waveforms and the SYNC signal
for the various drive modes of the PCF8566 are shown in Figure 27.
PCF8566_7
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 25 February 2009
34 of 48
NXP [ NXP ]
