PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
12. Dynamic characteristics
Table 20. Dynamic characteristics
VSS = 0 V; VDD = 2.5 V to 6.0 V; VLCD = VDD − 2.5 V to VDD − 6.0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. [1]
Symbol
Clock
fclk
Parameter
Conditions
Min
Typ
Max
Unit
[2]
clock frequency
normal mode;
125
21
200
31
315
48
kHz
kHz
V
DD = 5 V
power saving mode;
DD = 3.5 V
V
tclk(H)
tclk(L)
HIGH-level clock time
LOW-level clock time
1
1
-
-
-
-
-
-
-
µs
µs
ns
µs
µs
-
tPD(SYNC_N) SYNC propagation delay
400
-
tSYNC_NL
tPD(drv)
SYNC LOW time
1
-
driver propagation delay
with test loads;
LCD = VDD − 5 V
30
V
I2C-bus
tBUF
bus free time between a STOP and
START condition
4.7
-
-
µs
tHD;STA
tLOW
hold time (repeated) START condition
low period of the SCL clock
4.0
4.7
4.0
4.7
-
-
-
-
-
-
-
-
µs
µs
µs
µs
tHIGH
high period of the SCL clock
tSU;STA
set-up time for a repeated START
condition
tHD;DAT
tSU;DAT
tr
data hold time
0
-
-
-
-
-
-
ns
ns
µs
ns
µs
data set-up time
250
-
rise time of both SDA and SCL signals
fall time of both SDA and SCL signals
set-up time for STOP condition
-
1.0
300
-
tf
-
tSU;STO
4.7
[1] All timing values referred to VIH and VIL levels with an input voltage swing of VSS to VDD
[2] At fclk < 125 kHz, I2C-bus maximum transmission speed is derated.
.
PCF8566_7
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 25 February 2009
31 of 48
NXP [ NXP ]
