PCF8563
NXP Semiconductors
Real-time clock/calendar
9.5 I2C-bus protocol
9.5.1 Addressing
Before any data is transmitted on the I2C-bus, the device which should respond is
addressed first. The addressing is always carried out with the first byte transmitted after
the start procedure.
The PCF8563 acts as a slave receiver or slave transmitter. Therefore the clock signal SCL
is only an input signal, but the data signal SDA is a bidirectional line.
Two slave addresses are reserved for the PCF8563:
Read: A3h (10100011)
Write: A2h (10100010)
The PCF8563 slave address is illustrated in Figure 18.
1
0
1
0
0
0
1
R/W
group 2
group 1
mce189
Fig 18. Slave address
9.5.2 Clock and calendar READ or WRITE cycles
The I2C-bus configuration for the different PCF8563 READ and WRITE cycles is shown in
Figure 19, Figure 20 and Figure 21. The register address is a 4-bit value that defines
which register is to be accessed next. The upper four bits of the register address are not
used.
acknowledgement
from slave
acknowledgement
from slave
acknowledgement
from slave
S
SLAVE ADDRESS
0
A
REGISTER ADDRESS
A
DATA
A
P
R/W
n bytes
auto increment
memory register address
013aaa346
Fig 19. Master transmits to slave receiver (WRITE mode)
PCF8563
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 10 — 3 April 2012
26 of 50
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