PCF8563
NXP Semiconductors
Real-time clock/calendar
9.6 Interface watchdog timer
t < 1 s
data
START
SLAVE ADDRESS DATA DATA
STOP
WD timer
WD timer tracking
time
counters
running
time counters frozen
running
013aaa420
a. Correct data transfer: read or write
1 s < t < 2 s
data transfer fail
data
START
SLAVE ADDRESS
running
DATA DATA
WD timer
WD timer tracking
time counters frozen
WD trips
time
counters
running
013aaa421
b. Incorrect data transfer; read or write
Fig 22. Interface watchdog timer
During read/write operations, the time counting circuits are frozen. To prevent a situation
where the accessing device becomes locked and does not clear the interface, the
PCF8563 has a built in watchdog timer. Should the interface be active for more than 1 s
from the time a valid slave address is transmitted, then the PCF8563 will automatically
clear the interface and allow the time counting circuits to continue counting. The watchdog
will trigger between 1 s and 2 s after receiving a valid slave address. Each time the
watchdog period is exceeded, 1 s will be lost from the time counters.
The watchdog is implemented to prevent the excessive loss of time due to interface
access failure e.g. if main power is removed from a battery backed-up system during an
interface access.
PCF8563
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 10 — 3 April 2012
28 of 50
NXP [ NXP ]
