PCF8563
NXP Semiconductors
8.11 Reset
Real-time clock/calendar
The PCF8563 includes an internal reset circuit which is active whenever the oscillator is
stopped. In the reset state the I2C-bus logic is initialized including the address pointer and
all registers are set according to Table 27. I2C-bus communication is not possible during
reset.
Table 27. Register reset value[1]
Address Register name
Bit
7
0
0
1
x
6
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
5
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
4
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
3
1
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
2
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
0
0
x
x
x
x
x
x
x
x
x
x
x
0
1
x
0
0
0
x
x
x
x
x
x
x
x
x
x
x
0
1
x
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
Control_status_1
Control_status_2
VL_seconds
Minutes
Hours
x
Days
x
Weekdays
x
Century_months
Years
x
x
Minute_alarm
Hour_alarm
Day_alarm
Weekday_alarm
CLKOUT_control
Timer_control
Timer
1
1
1
1
1
0
x
[1] Registers marked x are undefined at power-up and unchanged by subsequent resets.
8.11.1 Power-On Reset (POR) override
The POR duration is directly related to the crystal oscillator start-up time. Due to the long
start-up times experienced by these types of circuits, a mechanism has been built in to
disable the POR and hence speed up on-board test of the device. The setting of this
mode requires that the I2C-bus pins, SDA and SCL, are toggled in a specific order as
shown in Figure 13. All timings are required minimums.
Once the override mode has been entered, the device immediately stops, being reset,
and normal operation may commence i.e. entry into the EXT_CLK test mode via I2C-bus
access. The override mode may be cleared by writing logic 0 to TESTC. TESTC must be
set to logic 1 before re-entry into the override mode is possible. Setting TESTC to logic 0
during normal operation has no effect except to prevent entry into the POR override
mode.
PCF8563
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 10 — 3 April 2012
22 of 50
NXP [ NXP ]
