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PCF8563TS/4 参数 Datasheet PDF下载

PCF8563TS/4图片预览
型号: PCF8563TS/4
PDF下载: 下载PDF文件 查看货源
内容描述: 实时时钟/日历 [Real-time clock/calendar]
分类和应用: 时钟
文件页数/大小: 50 页 / 492 K
品牌: NXP [ NXP ]
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PCF8563  
NXP Semiconductors  
Real-time clock/calendar  
13. Dynamic characteristics  
Table 30. Dynamic characteristics  
VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; fosc = 32.768 kHz; quartz Rs = 40 k; CL = 8 pF; unless otherwise  
specified.  
Symbol  
Oscillator  
COSCO  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
capacitance on pin OSCO  
15  
-
25  
35  
-
pF  
fosc/fosc  
relative oscillator frequency variation  
VDD = 200 mV;  
Tamb = 25 C  
0.2  
ppm  
Quartz crystal parameters (f = 32.768 kHz)  
Rs  
series resistance  
load capacitance  
trimmer capacitance  
-
-
-
-
100  
12.5  
25  
k  
pF  
pF  
[1]  
CL  
parallel  
7
5
Ctrim  
external;  
on pin OSCI  
CLKOUT output  
[2]  
[5]  
CLKOUT  
duty cycle on pin CLKOUT  
-
50  
-
%
I2C-bus timing characteristics (see Figure 28)[3][4]  
fSCL  
SCL clock frequency  
-
-
-
-
-
-
400  
kHz  
s  
tHD;STA  
tSU;STA  
tLOW  
tHIGH  
tr  
hold time (repeated) START condition  
set-up time for a repeated START condition  
LOW period of the SCL clock  
0.6  
0.6  
1.3  
0.6  
-
-
-
-
s  
s  
HIGH period of the SCL clock  
s  
rise time of both SDA and SCL signals  
standard-mode  
fast-mode  
-
-
-
-
-
1
s  
s  
s  
s  
-
0.3  
0.3  
-
tf  
fall time of both SDA and SCL signals  
-
tBUF  
bus free time between a STOP and START  
condition  
1.3  
Cb  
capacitive load for each bus line  
data set-up time  
-
-
-
-
-
-
400  
pF  
ns  
ns  
s  
ns  
tSU;DAT  
tHD;DAT  
tSU;STO  
tw(spike)  
100  
0
-
data hold time  
-
set-up time for STOP condition  
spike pulse width  
0.6  
-
-
on bus  
50  
Ctrim COSCO  
[1] CL is a calculation of Ctrim and COSCO in series: CL  
=
.
-----------------------------------------  
Ctrim + COSCO  
[2] Unspecified for fCLKOUT = 32.768 kHz.  
[3] All timing values are valid within the operating supply voltage at ambient temperature and referenced to VIL and VIH with an input voltage  
swing of VSS to VDD  
.
[4] A detailed description of the I2C-bus specification is given in Ref. 11 “UM10204”.  
[5] I2C-bus access time between two STARTs or between a START and a STOP condition to this device must be less than one second.  
PCF8563  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 10 — 3 April 2012  
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