PCA9557
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with reset
0.7 × V
0.3 × V
DD
SDA
DD
t
t
t
t
SP
t
r
f
HD;STA
BUF
t
LOW
0.7 × V
0.3 × V
DD
SCL
DD
t
t
t
SU;STO
HD;STA
SU;STA
t
t
t
SU;DAT
HD;DAT
HIGH
P
S
Sr
P
002aaa986
Fig 21. Definition of timing on the I2C-bus
ACK or read cycle
START
SCL
SDA
30 %
t
rst
RESET
50 %
50 %
50 %
t
rec(rst)
t
w(rst)
t
rst
I/O configured
as inputs
IOn
50 %
002aad289
Fig 22. Definition of RESET timing
PCA9557
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 7 — 10 December 2013
17 of 30
NXP [ NXP ]
