Philips Semiconductors
2004 Sep 30
S
0
1
SCL
1
2
3
4
16-bit I
2
C and SMBus I/O port with interrupt
slave address
acknowledge
from slave
acknowledge
from slave
slave address
acknowledge
from slave
data from lower
or upper byte
of register
acknowledge
from master
0
0
A2 A1 A0
0
R/W
A
COMMAND BYTE
A
S
0
0
1
0
A2 A1 A0
1
R/W
A MSB
DATA
first byte
LSB
A
at this moment master-transmitter
becomes master-receiver and
slave-receiver becomes
slave-transmitter
data from upper
or lower byte of
register
no acknowledge
from master
MSB
DATA
last byte
LSB NA
P
SU01463
NOTE:
Transfer can be stopped at any time by a STOP condition.
Figure 8. READ from register
5
6
7
8
9
I0.x
I1.x
2
1
0
A
7
6
5
4
3
2
1
0
A
7
6
5
4
I0.x
3
2
1
0
A
7
6
5
4
I1.x
3
2
1
0
1
P
9
SDA
S
0
1
0
0
A2
A1
A0
1
R/W
A
7
6
5
4
3
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM MASTER
ACKNOWLEDGE
FROM MASTER
ACKNOWLEDGE
FROM MASTER
NON ACKNOWLEDGE
FROM MASTER
READ FROM PORT 0
DATA INTO PORT 0
READ FROM PORT 1
DATA INTO PORT 1
INT
t
IV
t
IR
PCA9555
Product data sheet
SU01464
NOTES:
Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode).
It is assumed that the command byte has previously been set to 00 (read input port port register).
Figure 9. READ input port register — scenario 1
PHILIPS [ NXP SEMICONDUCTORS ]
