Philips Semiconductors
Product data sheet
16-bit I
2
C and SMBus I/O port with interrupt
PCA9555
SIMPLIFIED SCHEMATIC OF I/Os
DATA FROM
SHIFT REGISTER
CONFIGURATION
REGISTER
DATA FROM
SHIFT REGISTER
D
FF
WRITE CONFIGURATION
PULSE
WRITE PULSE
C
K
Q
D
FF
I/O PIN
C
K
Q
Q2
Q
Q
Q1
100 kΩ
OUTPUT PORT
REGISTER DATA
V
DD
OUTPUT
PORT
REGISTER
INPUT PORT
REGISTER
D
FF
READ PULSE
C
K
Q
Q
V
SS
INPUT PORT
REGISTER DATA
TO INT
DATA FROM
SHIFT REGISTER
WRITE
POLARITY
PULSE
D
FF
C
K
Q
POLARITY
REGISTER DATA
Q
POLARITY
INVERSION
REGISTER
SU01473
NOTE:
At Power-on Reset, all registers return to default values.
Figure 4. Simplified schematic of I/Os
I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off,
creating a high impedance input with a weak pull-up to V
DD
. The
input voltage may be raised above V
DD
to a maximum of 5.5 V.
If the I/O is configured as an output, then either Q1 or Q2 is on,
depending on the state of the Output Port register. Care should be
exercised if an external voltage is applied to an I/O configured as an
output because of the low impedance path that exists between the
pin and either V
DD
or V
SS
.
2004 Sep 30
5
PHILIPS [ NXP SEMICONDUCTORS ]
