2004 Sep 30
10
Philips Semiconductors
16-bit I
2
C and SMBus I/O port with interrupt
SCL
1
2
3
4
5
6
7
8
9
I0.x
I1.x
A
DATA 10
A
I0.x
DATA 03
A
I1.x
DATA 12
1
P
SDA
S
0
1
0
0
A2
A1
A0
1
R/W
A
DATA 00
ACKNOWLEDGE
FROM SLAVE
t
ph
ACKNOWLEDGE
FROM MASTER
ACKNOWLEDGE
FROM MASTER
t
ps
ACKNOWLEDGE
FROM MASTER
NON ACKNOWLEDGE
FROM MASTER
READ FROM PORT 0
DATA INTO PORT 0
DATA 00
DATA 01
t
ph
DATA 02
DATA 03
t
ps
READ FROM PORT 1
DATA INTO PORT 1
DATA 10
DATA 11
DATA 12
INT
t
IV
t
IR
SU01651
NOTES:
Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode).
It is assumed that the command byte has previously been set to 00 (read input port port register).
Figure 10. READ input port register — scenario 2
PCA9555
Product data sheet
PHILIPS [ NXP SEMICONDUCTORS ]
