Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
P87C552
!********************************************************************************************************
! SI01 EQUATE LIST
!********************************************************************************************************
!********************************************************************************************************
! LOCATIONS OF THE SI01 SPECIAL FUNCTION REGISTERS
!********************************************************************************************************
00D8
00D9
00DA
00DB
S1CON
S1STA
S1DAT
S1ADR
–0xd8
–0xd9
–0xda
–0xdb
00A8
00B8
IEN0
IP0
–0xa8
–02b8
!********************************************************************************************************
! BIT LOCATIONS
!********************************************************************************************************
00DD
00BD
STA
SI01HP
–0xdd
–0xbd
! STA bit in S1CON
! IP0, SI01 Priority bit
!********************************************************************************************************
! IMMEDIATE DATA TO WRITE INTO REGISTER S1CON
!********************************************************************************************************
00D5
00C5
00C1
00E5
ENS1_NOTSTA_STO_NOTSI_AA_CR0
ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0
ENS1_NOTSTA_NOTSTO_NOTSI_NOTAA_CR0
ENS1_STA_NOTSTO_NOTSI_AA_CR0
–0xd5
–0xc5
–0xc1
–0xe5
! Generates STOP
! (CR0 = 100kHz)
! Releases BUS and
! ACK
! Releases BUS and
! NOT ACK
! Releases BUS and
! set STA
!********************************************************************************************************
! GENERAL IMMEDIATE DATA
!********************************************************************************************************
0031
00A0
OWNSLA –0x31
! Own SLA+General Call
! must be written into S1ADR
! EA+ES1, enable SIO1 interrupt
! must be written into IEN0
! select PAG1 as HADD
! SLA+W to be transmitted
! SLA+R to be transmitted
! Select Register Bank 3
ENSI01
–0xa0
0001
00C0
00C1
0018
PAG1
SLAW
SLAR
–0x01
–0xc0
–0xc1
SELRB3 –0x18
!********************************************************************************************************
! LOCATIONS IN DATA RAM
!********************************************************************************************************
0030
0038
0040
0048
MTD
MRD
SRD
STD
–0x30
–0x38
–0x40
–0x48
! MST/TRX/DATA base address
! MST/REC/DATA base address
! SLV/REC/DATA base address
! SLV/TRX/DATA base address
0053
BACKUP
–0x53
! Backup from NUMBYTMST
! To restore NUMBYTMST in case
! of an Arbitration Loss.
! Number of bytes to transmit
! or receive as MST.
! Contains SLA+R/W to be
! transmitted.
! High Address byte for STATE 0
! till STATE 25.
0052
0051
0050
NUMBYTMST –0x52
SLA
–0x51
–0x50
HADD
52
1999 Mar 30